Sundance SMT335E - Manual (Page 26)

Version 1.5 Page 26 of 53 SMT335E SMT375E User Manual
SDB Initialisation
The SMT335E SDBs have been designed to allow their use with older, unidirectional
SDBs. When the processor comes out of reset, an SDB will be configured as a
receiver. It can be set to be a transmitter by the DSP, providing the other end of the
bus is not configured as a transmitter.
Initially the SDB clock is stopped; it will start running when the first transfer is
initiated. If the SDB receives 5 clock edges it will be locked as a receiver and will only
become a transmitter as the result of the normal data transfer protocols (using REQ
and ACK signals as described in the SDB specification). As long as the clock lines
are not being driven, the SDB can be switched to a transmitter by setting the TRANS
bit in its control and status register.
When connecting two SDBs together you must make one of them a transmitter
before transfers will work; this is independent of the actual direction of the first
transfer. Neither trying to switch an SDB that has already been connected to a
transmitter nor changing TRANS once the clocks have started running will have any
effect.
When two SMT335E SDBs are connected it does not matter which end is set to be a
transmitter. When connecting an SMT335E to an older, input-only SDB, the
SMT335E SDB must be made a transmitter.
Suspending SDB transmission
To prevent loss of data, transmission will normally be suspended when a receiving
FIFO becomes full. In certain circumstances, allowing the transmission to continue
may be more important than losing data. This can be achieved by setting the DIS bit
in the control and status register.
When DIS is set, a reading SDB will never indicate that its FIFO is full and will
continue reading; a writing SDB will ignore a full signal from the receiver and
continue to send data.
Bus exchange
The SDB allows fully bi-directional transmission but, for maximum throughput, bus
turn-around should be reduced to the minimum. The priority of bus ownership can be
selected using the PRI bit. If PRI is 1 there is no priority: a transmitter will release the
bus as soon as a receiver requests it. If PRI is 0 the transmitter will hold the bus as
long as its output FIFO contains data, even if the receiver is requesting the bus.