Sundance SMT335E - Manual (Page 28)

Version 1.5 Page 28 of 53 SMT335E SMT375E User Manual
Global bus
The SMT335E provides a global bus that is compatible with the TIM standard. A dual
port RAM (DPR) is used as intermediate storage for transfers of data frames between
the C6000 and an external device on the global bus; each frame can have up to 256
32-bit words. All transfers start from the first word of the DPR. For debugging, the
POS field in the Global Bus Control Register will tell you which word of the frame is
being transmitted.
When writing, the C6000 writes a frame to the DPR and the FPGA then sends it
across the global bus to the external device. When reading, the external device
writes the frame across the global bus to the DPR and the C6000 then reads it.
The FPGA needs to know when the C6000 has finished transferring data to or from
the DPR. It determines this by observing a trigger word in the DPR, usually the final
word of a frame. The FPGA hands control of the DPR to the global bus when the
C6000 accesses the trigger word
1 . You define the trigger word by setting the
Operation Register TRIGGER field to the number of words in the frame minus one.
A Global Bus Address Register is used to hold the address to be presented to the
external device. You may elect for this address to be incremented by 1 after each
word has been moved between the DPR and the external device; you do this by
setting the INC bit in the Global Bus Control Register.
Writing to the Global Bus
First specify the trigger value in the Operation Register. For example, if your frame
size were 128 words, you would write a trigger value of 127. At the same time that
you set the trigger you must also set the OPERATION bit to 1, indicating that data is
to go from the C6000 to the global bus.
You may now write your data to the DPR. As soon as the FPGA detects a write to the
trigger word, it will send the data in the DPR out to the external device.
Once the complete frame has been sent, the FPGA will signal an interrupt condition
by setting the DONE flag in the Global Bus Control Register. You can use this
condition to interrupt the C6000 or synchronise a DMA transfer.
1 In fact, the actual trigger condition is that bits 9–2 of the address used to access the DPR are equal
to the trigger value. The FPGA ignores bits 17–10 and bits 1–0 of the address used to access the
DPR. This means that there are many trigger locations in the address space allocated to the DPR.