Avago Technologies LSI8751D - Manual (Page 257)

PCI and External Memory Interface Timing Diagrams 7-21
Figure 7.13 External Memory Read (Cont.)
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C875)
STOP/
(Driven by LSI53C875)
DEVSEL/
(Driven by LSI53C875)
AD
(Driven by Master-Addr;
C_BE/
(Driven by Master)
FRAME/
(Driven by Master)
Data Driven by Memory)
LSI53C875-Data)
LSI53C875-Data)
MAD
(Addr Drvn by LSI53C875;
MAS1/
(Driven by LSI53C875)
MAS0/
(Driven by LSI53C875)
MCE/
(Driven by LSI53C875)
MOE/
(Driven by LSI53C875)
MWE/
(Driven by LSI53C875)
GPIO_MAS2/
(Driven by LSI53C875)
11 12 13 14 15 16 17 18 19 20
Data
Out
t
3
t
2
t
2
21
t
3
Out
Data
In
t
19
t
17
t
3
t
3
t
14
t
15
t
16