Avago Technologies LSI8751D - Manual (Page 29)

Prefetching SCRIPTS Instructions 2-5
Step 1. Set the SCLK Doubler Enable bit ( SCSI Test One (STEST1) ,
bit 3).
Step 2. Wait 20
µ
s.
Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit ( SCSI
Test Three (STEST3), bit 5).
Step 4. Set the clock conversion factor using the SCF and CCF fields
in the
SCSI Control Three (SCNTL3) register.
Step 5. Set the SCLK Doubler Select bit ( SCSI Test One (STEST1) ,
bit 2).
Step 6. Clear the Halt SCSI Clock bit.
2.3 Prefetching SCRIPTS Instructions
When enabled by setting the Prefetch Enable bit in the DMA Control
(DCNTL) register, the prefetch logic in the LSI53C875 fetches 8 Dwords
of instructions. The prefetch logic automatically determines the maximum
burst size that it can perform, based on the burst length as determined
by the values in the
DMA Mode (DMODE) register. If the unit cannot
perform bursts of at least four Dwords, it disables itself. While the
LSI53C875 is prefetching SCRIPTS instructions, the PCI Cache Line
Size register value does not have any effect and the Read Line, Read
Multiple, and Write and Invalidate commands are not used.
The LSI53C875 may flush the contents of the prefetch unit under certain
conditions, listed below, to ensure that the chip always operates from the
most current version of the software. When one of these conditions
apply, the contents of the prefetch unit are automatically flushed.
•
On every Memory Move instruction. The Memory Move instruction is
often used to place modified code directly into memory. To make
sure that the chip executes all recent modifications, the prefetch unit
flushes its contents and loads the modified code every time an
instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the next 8 Dwords. For more
information on this instruction, refer to
Chapter 6, “Instruction Set of
the I/O Processor.”