Avago Technologies LSI8751D - Manual (Page 306)

IX-2 Index
DIF bit 5-73
differential mode
DIFFSENS 4-19
direction control pins 4-16
operation 2-20
SCSI differential mode bit 5-73
DIFFSENS SCSI signal 7-3
disable halt on parity error or ATN 5-7
disable single initiator response bit 5-76
DMA byte counter register 5-44
DMA command register 5-45
DMA control register 5-51
DMA core 2-2
DMA direction bit 5-42
DMA FIFO bits 5-43
DMA FIFO empty bit 5-23
DMA FIFO register 5-39
DMA FIFO size bit 5-42
DMA interrupt enable register 5-50
DMA interrupt pending bit 5-34
DMA mode register 5-47
DMA next address register 5-45
DMA SCRIPTS pointer register 5-46
DMA SCRIPTS pointer save register 5-46
DMA status register 5-23
DMODE register 5-47
DNAD register 5-45
DSA register 5-31
DSP register 5-46
DSPS register 5-46
DSTAT register 5-23
E
enable parity checking bit 5-5
enable read line bit 5-49
enable read multiple bit 5-49
enable response to reselection bit 5-14
enable response to selection bit 5-14
enable wide SCSI bit 5-12
encoded chip SCSI ID 5-14
encoded destination SCSI ID bit 5-22
encoded destination SCSI ID bits 5-18
extend SREQ/SACK filtering bit 5-74
external memory interface 2-6
,
2-7
configuration 2-7
flash ROM updates 2-6
GPIO4 bit 5-19
multiple byte accesses 7-13
slow memory 2-8
system requirements 2-6
extra clock cycle of data setup bit 5-6
F
fetch enable 5-63
fetch pin mode bit 5-38
FIFO byte control bits 5-41
FIFO flags bits 5-27
,
5-30
flush DMA FIFO bit 5-37
FMT 5-34
function complete bit 5-54
,
5-57
G
general purpose pin control register 5-63
general purpose register 5-19
general purpose timer expired bit 5-56
,
5-59
general purpose timer period bits 5-68
general purpose timer scale factor bit 5-66
GPCNTL register 5-63
GPIO enable bit 5-63
GPIO[4:0] bits 5-19
GPREG register 5-19
H
halt SCSI clock bit 5-76
handshake-to-handshake timer bus activity enable bit 5-66
handshake-to-handshake timer expired bit 5-56
,
5-59
handshake-to-handshake timer period bit 5-64
high impedance mode bit 5-40
I
I/O instructions 6-12
illegal instruction detected bit 5-24
immediate arbitration bit 5-8
input 4-6
instruction prefetching 2-5
prefetch enable bit 5-51
prefetch flush bit 5-51
prefetch unit flushing 2-5
instructions
block move 6-5
I/O 6-12
load and store 6-37
memory move 6-33
read/write 6-21
transfer control 6-26
internal RAM, see also SCRIPTS RAM 2-3
interrupt status register 5-31
interrupt-on-the-fly bit 5-33
interrupts
fatal vs. nonfatal interrupts 2-30
halting 2-33
IRQ disable bit 2-30
masking 2-31
sample interrupt service routine 2-33
stacked interrupts 2-32
IRQ disable bit 5-52
IRQ mode bit 5-52
ISTAT register 5-31
J
JTAG support 2-10
L
last disconnect bit 5-30
latched SCSI parity bit 5-28
latched SCSI parity for SD[15:8] bit 5-30
load and store instructions 6-37
no flush option 6-38
prefetch unit and store instructions 2-6
,
6-38
lost arbitration bit 5-27
LSI53C700 family compatibility bit 5-53