2 selection of cache line size, 3 alignment, Selection of cache line size – Avago Technologies LSI8751D User Manual
Page 69: Alignment
PCI Cache Mode
3-5
3.2.2 Selection of Cache Line Size
The cache logic selects a cache line size based on the values for the
burst size in the
register, bit 2 in the
register, and the PCI
register.
Note:
The LSI53C875 does not automatically use the value in the
PCI
register as the cache line size value.
The chip scales the value of the
register
down to the nearest binary burst size allowed by the chip
(2, 4, 8, 16, 32, 64, or 128), compares this value to the
burst size defined by the values of the
register and bit 2 of the
register, then selects the smallest as the value for the
cache line size. The LSI53C875 uses this value for all burst
data transfers.
3.2.3 Alignment
The LSI53C875 uses the calculated line size value to monitor the current
address for alignment to the cache line size. When it is not aligned, the
chip attempts to align to the cache boundary by using a “smart aligning”
scheme. This means that it attempts to use the largest burst size
possible that is less than the cache line size, to reach the cache
boundary quickly with no overflow. This process is a stepping
mechanism that steps up to the highest possible burst size based on the
current address.
The stepping process begins at a 4 Dword boundary. The LSI53C875 will
first try to align to a 4 Dword boundary (0x00, 0x010, 0x020, etc.) by
using single Dword transfers (no bursting). Once this boundary is
reached the chip evaluates the current alignment to various burst sizes
allowed, and selects the largest possible as the next burst size, while not
exceeding the cache line size. The chip then issues this burst, and
reevaluates the alignment to various burst sizes, again selecting the
largest possible while not exceeding the cache line size, as the next
burst size. This stepping process continues until the chip reaches the
cache line size boundary or runs out of data. Once a cache line boundary
is reached, the chip uses the cache line size as the burst size from then
on, except in the case of multiples (explained below). The alignment
process is finished at this point.