RME Fireface UCX II 40-Channel USB-B Audio/MIDI Interface - Manual (Page 115)

User's Guide Fireface UCX II © RME
115
40.6 Noise level in DS / QS Mode
The outstanding signal to noise ratio of the Fireface UCX II AD-converters can be verified even
without expensive test equipment, by using record level meters of various software. But when
activating the DS and QS mode, the displayed noise level will rise from -113 dB to -105 dB at 96
kHz, and
–79 dB at 192 kHz. This is not a failure. The software measures the noise of the whole
frequency range, at 96 kHz from 0 Hz to 48 kHz (RMS unweighted), at 192 kHz from 0 Hz to 96
kHz.
When limiting the measurement range from 20 Hz to 20 kHz (so called audio bandpass) the
value would be -113 dB again. This can be verified with RME's
DIGICheck . The function Bit
Statistic & Noise measures the noise floor by Limited Bandwidth , ignoring DC and ultrasound.
The reason for this behaviour is the noise shaping technology of the analog to digital converters.
They move all noise and distortion to the in-audible higher frequency range, above 24 kHz.
That’s how they achieve their outstanding performance and sonic clarity. Therefore the noise is
slightly increased in the ultrasound area. High-frequent noise has a high energy. Add the dou-
bled (quadrupled) bandwidth, and a wideband measurement will show a significant drop in SNR,
while the human ear will notice absolutely no change in the audible noise floor.
40.7 SteadyClock
The SteadyClock technology of the Fireface UCX II guarantees an excellent performance in all
clock modes. Thanks to a highly efficient jitter suppression, the AD- and DA-conversion always
operates on highest sonic level, being completely independent from the quality of the incoming
clock signal.
SteadyClock has been originally
de-
veloped to gain a stable and
clean clock from the heavily
jit-
tery MADI data signal (the em- bed-
ded MADI clock suffers from
about 80 ns jitter). Using the
Fireface's input signals AES and
ADAT, you'll most probably nev-
er
experience such high jitter val- ues.
But SteadyClock is not only
ready for them, it would handle
them
just on the fly.
Common interface jitter values
in
real world applications are below 10
ns, a very good value is less than 2 ns.
The screenshot shows an extremely jittery SPDIF signal of about 50 ns jitter (top graph, yellow).
SteadyClock turns this signal into a clock with less than 2 ns jitter (lower graph, blue). The signal
processed by SteadyClock is of course not only used internally, but also used to clock the digital
outputs. Therefore the refreshed and jitter-cleaned signal can be used as reference clock with-
out hesitation.