11 usual dram write cycles – FUJITSU MB91F109 FR30 User Manual

Page 203

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4.17 Bus Timing

4.17.11 Usual DRAM Write Cycles

This section provides usual DRAM write cycle timing charts.

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Usual DRAM Write Cycle Timing Charts

❍

Bus width: 16 bits, access: half-words

Figure 4.17-21 Example 1 of Usual DRAM Write Cycle Timing Chart

Q1

Q2

Q3

Q4

Q5

CLK

1CAS/2WE
A24-00

X

#0 row.adr.

#0 col.adr

D31-24

#0

D23-16

#1

RAS
CAS
WEL
WEH

2CAS/1WE
A24-00

X

#0 row.adr.

#0 col.adr

D31-24

#0

D23-16

#1

RAS
CASL
CASH
WE

1)

2)

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