FUJITSU MB91F109 FR30 - Manual (Page 271)

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10.1 Overview of UART
■ UART Block Diagram
Figure 10.1-2 is a UART block diagram.
Figure 10.1-2 UART Block Diagram
SC
SI
SO
SIDR SODR
MD1 PEN PE
MD0 P ORE
SBL FRE
SMR SCR
CL
SSR
RDRF
CS0 A/D TDRE
REC
SCKE RXE RIE
SOE TXE TIE
R - BUS
Control signal
Reception interrupt
(to CPU)
From U-TIMER
External clock
Clock
selection
circuit Reception clock
Transmission clock
SC (clock)
Transmision interrupt
(to CPU)
(received data)
Reception
control circuit
Start bit
detection circuit
Reception
bit counter
Reception
parity counter
Transmission
control circuit
Tranmission
start circuit
Tranmission
bit counter
Tranmission
parity counter
(Transmit data)
Reception status
check circuit
Reception shifter
End of reception
Transmission shifter
Start of transmission
Reception error generation
signal for DMA (to DMAC)
register register register
Control signal