FUJITSU MB91F109 FR30 - Manual (Page 239)

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6.4 External Level Register (ELVR)
6.4 External Level Register (ELVR)
The external level register (ELVR) selects the request detection mode.
■ External Level Register (ELVR)
The configuration of the external level register (ELVR) is shown below:
The external level register (ELVR) selects the request detection mode.
Two bits each are assigned to INT0 to INT3 and defined as shown in Table 6.4-1.
Suppose the level is selected for the request detection mode. If input is in the active level even
after each EIRR bit is cleared, the corresponding bit is set again.
NMI is always detected at its falling edge (except when it stops).
When it stops, it is detected at the L level.
7 6 5 4 3 2 1 0
ELVR
Address:000099
H
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000 R/W
Initial value Access
Table 6.4-1 External Interrupt Request Mode
LBx LAx Request detection mode
0 0 L level
0 1 H level
1 0 Rising edge
1 1 Falling edge