FUJITSU MB91F109 FR30 - Manual (Page 54)

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CHAPTER 2 CPU
2.1 CPU Architecture
The FR30 CPU is a high performance core that uses the RISC architecture and
supports advanced functional instructions geared to embedding applications.
■ Characteristics of CPU Architecture
❍ RISC architecture
• Basic instruction: One instruction per cycle
❍ 32-bit architecture
• 32-bit general-purpose register x 16
❍ Linear 4-gigabyte memory space
❍ Internal operation of the adder
• Addition of 32 bits x 32 bits: Five cycles
• Addition of 16 bits x 16 bits: Three cycles
❍ Enhanced interrupt processing function
• High-speed response (six cycles)
• Support of multiple concurrent interrupts
• Level mask function (16 levels)
❍ Enhanced I/O operation instructions
• Inter-memory transfer instruction
• Bit processing instruction
❍ High coding efficiency
• Basic instruction word length: 16 bits
❍ Low power consumption
• Sleep mode and stop mode