FUJITSU MPB3052AT - Manual (Page 141)

C141-E045-02EN 5 - 76
5.6.2 Single word DMA data transfer
Figure 5.10 show the single word DMA data transfer timing between the device and the host
system.
tF tE
tH tG
tJ
tD
tI
tC
t0
Read data
DD0-DD15
Write data
DD0-DD15
DIOR-/DIOW-
DMACK-
DMARQ
Symbol Timing parameter Min. Max. Unit
t0 Cycle time 240 — ns
tC Delay time from DMACK assertion to DMARQ negation — 80 ns
tD Pulse width of DIOR-/DIOW- 120 — ns
tE Data setup time for DIOR- — 60 ns
tF Data hold time for DIOR- 5 — ns
tG Data setup time for DIOW- 35 — ns
tH Data hold time for DIOW- 20 — ns
tI DMACK setup time for DIOR-/DIOW- 0 — ns
tJ DMACK hold time for DIOR-/DIOW- 0 — ns
Figure 5.10 Single word DMA data transfer timing