Motorola SSETM 5000 - Manual (Page 32)

November 11, 2004 6881094C12-A
2-10 Theory of Operation: Transceiver Board
2.4.2.1.2 LNA (Low-Noise Amplifier)
The SSE 5000 radio uses a discrete transistor for the low-noise amplifier (Q430). A feedback
network between the collector and base improves stability and gain balance across the frequency
band. Input and output LC networks match the LNA impedance to 50 ohms.
A diode limiter (D400) protects the amplifier damage by strong input signals.
2.4.2.1.3 Mixer
The mixer (U470) down-converts the received RF to the first intermediate frequency (IF). The IF is
73.35 MHz. Low-side LO injection is used. Transformers are used as baluns to convert signals from
single-ended to balanced at pins MI, MIX, LO, and LOX. An output transformer converts the
balanced signal at pins MO and MOX to a single-ended output.
2.4.2.1.4 IF Filter
The IF filter (FL400) is a leadless, surface-mount, 3-pole, quartz crystal filter. This narrow bandpass
filter gives the radio its adjacent-channel and alternate-channel rejection performance.
Input and output LC networks match the filter impedance to 50 ohms.
2.4.2.2 Receiver Back-End
NOTE: Refer to Figure 2-2 for the receiver block diagram and Figure 12-3 for the receiver back-end
schematic.
The receiver back-end, which consists of the Abacus III (AD9874 IF digitizing subsystem) IC and its
associated circuitry, processes the down-converted IF signal to produce digital data for final
processing by the VOCON DSP.
2.4.2.2.1 Abacus III IC U500
The AD9874 is a general-purpose, IF subsystem that digitizes a low-level 10–300 MHz IF input with
a bandwidth up to 270 kHz. The output of the Abacus III IC is SSI data to the VOCON.
The signal chain of the AD9874 consists of a low-noise amplifier, a mixer, a bandpass sigma-delta
A/D converter, and a decimation filter with programmable decimation factor. An automatic gain
control (AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high
dynamic range and inherent anti-aliasing provided by the bandpass sigma-delta converter allow the
AD9874 to cope with blocking signals 80 dB stronger than the desired signal.
Auxiliary blocks include frequency synthesizers for the second LO and sampling clock LO, as well as
an SPI port. The second LO uses a discrete external loop filter and VCO. The clock oscillator has an
external loop filter and resonator.