IBM Z10 BUISNESS CLASS Z10 BC - Manual (Page 17)

z10 BC Performance
The performance design of the z/Architecture can enable
the server to support a new standard of performance for
applications through expanding upon a balanced system
approach. As CMOS technology has been enhanced to
support not only additional processing power, but also
more PUs, the entire server is modifi ed to support the
increase in processing power. The I/O subsystem supports
a greater amount of bandwidth than previous generations
through internal changes, providing for larger and faster
volume of data movement into and out of the server. Sup-
port of larger amounts of data within the server required
improved management of storage confi gurations, made
available through integration of the operating system and
hardware support of 64-bit addressing. The combined bal-
anced system design allows for increases in performance
across a broad spectrum of work.
Large System Performance Reference
IBM’s Large Systems Performance Reference (LSPR)
method is designed to provide comprehensive
z/Architecture processor capacity ratios for different con-
fi gurations of Central Processors (CPs) across a wide
variety of system control programs and workload envi-
ronments. For z10 BC, z/Architecture processor capacity
identifi er is defi ned with a (A0x-Z0x) notation, where x is
the number of installed CPs, from one to fi ve. There are
a total of 26 subcapacity levels, designated by the letters
A through Z.
In addition to the general information provided for z/OS
V1.9, the LSPR also contains performance relationships for
z/VM and Linux operating environments.
Based on using an LSPR mixed workload, the perfor-
mance of the z10 BC (2098) Z01 is expected to be:
• up to 1.4 times that of the z9 BC (2096) Z01.
Moving from a System z9 partition to an equivalently sized
System z10 BC partition, a z/VM workload will experience
an ITR ratio that is somewhat related to the workload’s
instruction mix, MP factor, and level of storage over com-
mitment. Workloads with higher levels of storage over
commitment or higher MP factors are likely to experience
lower than average z10 BC to z9 ITR scaling ratios. The
range of likely ITR ratios is wider than the range has been
for previous processor migrations.
The LSPR contains the Internal Throughput Rate Ratios
(ITRRs) for the z10 BC and the previous-generation
zSeries processor families based upon measurements
and projections using standard IBM benchmarks in a con-
trolled environment. The actual throughput that any user
may experience will vary depending upon considerations
such as the amount of multiprogramming in the user’s job
stream, the I/O confi guration, and the workload processed.
Therefore no assurance can be given that an individual
user will achieve throughput improvements equivalent
to the performance ratios stated. For more detailed per-
formance information, consult the Large Systems Perfor-
mance Reference (LSPR) available at:
http://www.ibm.com/servers/eserver/zseries/lspr/.
CPU Measurement Facility
The CPU Measurement Facility is a hardware facility which
consists of counters and samples. The facility provides a
means to collect run-time data for software performance
tuning. The detailed architecture information for this facility
can be found in the System z10 Library in Resource Link ™ .
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