IBM 990 - Manual (Page 18)

6 IBM
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zSeries 990 Technical Guide
Coupling Links, FICON, and OSA). In June 1997, IBM announced increased support - up to
15 logical partitions on Generation 3 and Generation 4 servers.
The evolution continues and IBM is announcing support for 30 logical partitions. This support
is exclusive to z990 and z890 models.
MCM technology
The z990 12-PU MCM is smaller and more capable than the z900’s 20-PU MCM. It has
16 chips, compared to 35 for the z900. The total number of transistors is over 3 billion,
compared with approximately 2.5 billion for the z900. With this amazing technology
integration comes improvements in chip-to-substrate and substrate-to-board connections.
The z990 module uses a connection technology, Land Grid Arrays (LGA), pioneered by the
pSeries® in the p690 and the i890. LGA technology enables the z990 substrate, with only
53% of the surface area of the z900 20 PU MCM substrate, to have 23% more I/Os from the
logic package.
Both the z900 and z990 have 101 layers in the glass ceramic substrate. The z990's substrate
is thinner, shortening the paths that signals must travel to reach their destination (another chip
or exiting the MCM). Inside the low dielectric glass ceramic substrate is 0.4 km of internal
wiring that interconnects the 16 chips that are mounted on the top layer of the MCM. The
internal wiring provides power and signal paths into and out of the MCM.
The MCM on the z990 offers flexibility in enabling spare PUs via the Licensed Internal Code
Configuration Control (LIC-CC) to be used for a number of different functions. These are:
A Central Processor (CP)
A System Assist Processor (SAP)
An Internal Coupling Facility (ICF)
An Integrated Facility for Linux (IFL)
A zSeries Application Assist Processor (zAAP)
The number of CPs and SAPs assigned for particular general purpose models depends on
the configuration. The number of spare PUs is dependent on how many CPs, SAPs, ICFs,
zAAPs, and IFLs are present in a configuration.
1.3.2 Memory
The minimum system memory on any model is 16 GB. Memory size can be increased in 8 GB
increments to a maximum of 64 GB per book or 256 GB for the entire CPC. Each book has
two memory cards, which come in three physical size cards: 8 GB, 16 GB, and 32 GB.
The z990 continues to employ storage size selection by Licensed Internal Code introduced on
the G5 processors. Memory cards installed may have more usable memory than required to
fulfill the machine order. LICCC will determine how much memory is used from each card.
1.3.3 Self-Timed Interconnect (STI)
An STI is an interface to the Memory Bus Adaptor (MBA), used to gather and send data. 12
STIs per z990 physical book is supported. Each of these STIs has a bidirectional bandwidth
of 2 GBps. The maximum instantaneous bandwidth per book is 24 GBps.
1.3.4 Channel Subsystem (CSS)
A new Channel Subsystem (CSS) structure was introduced with z990 to “break the barrier” of
256 channels. With the introduction of the new system structure and all of its scalability