IBM 990 - Manual (Page 48)

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zSeries 990 Technical Guide
Figure 2-11 MCM chip layout
2.1.8 The PU, SC, and SD chips
All chips use CMOS 9SG technology, except for the clock chip (CMOS 8S). CMOS 9SG is
state-of-the-art microprocessor technology based on eight-layer Copper Interconnections and
Silicon-On Insulator technologies. The chip’s lithography line width is 0.125 micron.
The eight PU chips come in two versions. The Processor Units (PUs) on the MCM in each
book are implemented with a mix of single-core and dual-core PU chips. Four single-core and
four dual-core chips are used, resulting in 12 PUs per MCM.
Eight PUs may be characterized for customer use, one per PU chip. The two standard SAPs
and two standard spares are initially allocated to the dual-core processor chips. Each core on
the chip runs at a cycle time of 0.83 nanoseconds. Each dual-core PU chip measures
14.1 x 18.9 mm and has 122 million transistors.
Each PU has a 512 KB on-chip Level 1 cache (L1) that is split into a 256 KB L1 cache for
instructions and a 256 KB L1 cache for data, providing large bandwidth.
SC chip
The L1 caches communicate with the L2 caches (SD chips) by two bi-directional 16-byte data
buses. There is a 2:1 bus/clock ratio between the L2 cache and the PU, controlled by the
Storage Controller (SC chip), that also acts as an L2 cache cross-point switch for L2-to-L2
ring traffic, L2-to-MSC traffic, and L2-to-MBA traffic. The L1-to-L2 interface is shared by two P
PU cores on a dual core PU chip.
MSC MSC
CLK
SD SD
SD
SD
SC
PU PU
PU
PU
PU PU
PU
PU