IBM 990 - Manual (Page 234)

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zSeries 990 Technical Guide
This implementation provides optimal performance and a more linear scalability to the z990
server. The results can be observed in the LSPR’s ITR values from the uniprocessor to the
32-way server.
8.7.2 Superscalar processors
The z990 server is the first generation of zSeries servers that uses superscalar processors. A
superscalar processor can execute multiple instructions per cycle, potentially providing better
performance than a sequential processor running at the same cycle time (or processor
frequency).
To exploit this parallel execution capability, the z990 server has implemented an improved
instruction scheduling. The instruction execution order is optimized to provide instruction
sequences that can operate in a multi-pipeline environment. The major enhancements are in
the e-business applications, such as WebSphere and other Java and C/C++ code.
Further exploitation can also be done on the software side. Compilers can be changed to
provide an optimized instruction scheduling to better exploit the superscalar design.
8.7.3 Integrated hardware and system assists
To achieve the required throughput and implement new functions while maintaining balanced
usage of system resources, integrated hardware and system assists are key.
zSeries Application Assist Processors (zAAPs)
The zSeries Application Assist Processors (zAAPs) are designed to operate asynchronously
with the CPs to execute Java programming under control of IBM Java Virtual Machine (JVM)
for logical partitions running z/OS. This can help reduce the demands and capacity
requirements on CPs that may be available for relocation to other zSeries workloads.
The IBM JVM processing cycles can be executed on the configured zAAPs with no
anticipated modifications to the Java applications. Execution of the JVM processing cycles on
a zAAP is a function introduced by the Software Developer’s kit (SDK) 1.4.1 for zSeries, z/OS
V1.6, and the Processor Resource/Systems Manager (PR/SM).
Cryptographic function on every Processor Unit (PU)
The z990 introduces the Cryptographic Assist Architecture (CAA) along with the CP Assist for
Cryptographic Function (CPACF), delivering cryptographic support on every Processor Unit
(PU) with DES and TDES data encryption/decryption and SHA-1 hashing.
This offers balanced use of system resources and provides unprecedented scalability (a z990
can have from one to 32 PUs, depending upon model) and data rates at 2X or more faster
than the CMOS Cryptographic Coprocessor Facility (CCF).
Since these cryptographic functions are implemented in each and every PU, the association
of cryptographic functions to specific PUs, as was done with previous generations of zSeries,
is eliminated.
Secure encrypted transactions with higher performance
PCIX Cryptographic Coprocessor (PCIXCC) FC 0868 is a replacement for the PCI
Cryptographic Coprocessor (PCICC) and the CMOS Cryptographic Coprocessor Facility that
were offered on z900. All of the equivalent PCICC functions that are implemented offer higher
performance. In addition, the functions on the CMOS Cryptographic Coprocessor Facility
used by known applications have also been implemented in the PCIXCC feature.