Intel ECB-870 - Manual (Page 19)

ECB-870
ECB-870 User’s Manual 7
USB host interface; 2 host controllers and supports 4 USB ports
Integrated LAN controller
System Management Bus (SMBus) compatible with most I2C devices; ICH2 has both
bus master and slave capability
AC ’97 2.1 compliant link for audio and telephony codecs; up to 6 channels (ICH2)
Low Pin Count (LPC) interface
FWH Interface (FWH Flash BIOS support)
Alert on LAN* (AOL and AOL2)
2.3.2 System Memory Interface
The MCH integrates a system memory SDRAM controller with a 64-bit wide interface and
twelve system memory clock signals.
The MCH includes support for:
Up to 2 GB of 200/266 MHz DDR SDRAM
DDR200/266 unbuffered 184 pin DDR SDRAM DIMMs
Maximum of 2 DIMMs, single-sided and/or double-sided
Configurable optional ECC
The two bank-select lines SBS[1:0] and the thirteen address lines (SMA[12:0]) allow the
MCH to support 64-bit wide DIMMs using 64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM
technologies.
While address lines SMA[9:0] determine the starting address for a burst, burst lengths are
fixed at four. Four chip selects SCS# lines allow a maximum of two rows with single-sided
SDRAM DIMMs and four rows with double-sided SDRAM DIMMs.
The MCH’s system memory controller targets CAS latencies of 2 and 2.5 clocks for
SDRAM. The MCH provides refresh functionality with a programmable rate (normal
SDRAM rate is 1 refresh/15.6 µs).