Intel ECB-870 - Manual (Page 67)

ECB-870
ECB-870 User’s Manual 55
4.5.4.1 DRAM Timing Selectable
If your DIMM memory has SPD (Serial Presence Detect) 8-pin IC on module, you can set
this option to “By SPD”. System will set your SDRAM clock and timing from the SPD IC. If
the option set as ”Manual”, DRAM clock and timing must be set from items below:
The choice: SPD, Manual.
4.5.4.2 SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. Do not reset this field from the default value specified by
the system designer. This controls the latency between the SDRAM read command and
the time that the data actually becomes available.
The choice: 1.5, 2, 2.5, 3, and Auto.
4.5.4.3 Active to Precharge delay
When you select “Manual” mode, you can set active to Precharge SDRAM timing delay.
The choice: 7, 6, 5, and Auto.
4.5.4.4 SDRAM RAS-to-CAS Delay
These are timing of SDRAM CAS Latency and RAS to CAS Delay, calculated by clocks.
They are important parameters affects SDRAM performance.
The choice: 3, 2.
4.5.4.5 SDRAM RAS Precharge Time
The RAS Recharge means the timing to inactive RAS and the timing for DRAM to do
recharge before next RAS can be issued.
The choice: 3, 2.
4.5.4.6 Memory Frequency For
When you select “Auto” mode, Allows DRAM PC 100 or PC 133 Data Integrity mode.
The choice: PC100, PC133, Auto.
4.5.4.7 DRAM Read Thermal Mgmt.
When you select “Manual” mode, you can set DRAM Read Thermal Mgmt.
The choice: Enable, Disable.
4.5.4.8 System BIOS Cacheable
Allows the system BIOS to be cached for faster system performance.
The choice: Enable, Disable.