SanDisk CompactFlash Extreme III - Manual (Page 48)

ATA Register Set and Protocol SanDisk CompactFlash Card OEM Product Manual
4.4 True IDE Mode Addressing
When a CompactFlash Memory Card is configured in the True IDE Mode the I/O decoding is
as listed in Table 4-5.
Table 4-5 True IDE Mode I/O Decoding
-CE2 -CE1 A2 A1 A0 -IORD=0 -IOWR=0
1 0 0 0 0 Even RD Data Even WR Data
1 0 0 0 1 Error Register Features
1 0 0 1 0 Sector Count Sector Count
1 0 0 1 1 Sector No. Sector No.
1 0 1 0 0 Cylinder Low Cylinder Low
1 0 1 0 1 Cylinder High Cylinder High
1 0 1 1 0 Select Card/Head Select Card/Head
1 0 1 1 1 Status Command
0 1 1 1 0 Alt Status Device Control
0 1 1 1 1 Drive Address Reserved
4.5 ATA Registers
In accordance with the PCMCIA specification: each of the registers below which is located at
an odd offset address may be accessed at its normal address and also the corresponding even
address (normal address -1) using data bus lines (D15-D8) when -CE1 is high and -CE2 is low
unless -IOIS16 is high (not asserted) and an I/O cycle is being performed.
4.5.1 Data Register (Address–1F0[170]; Offset 0, 8, 9)
The Data Register is a 16-bit register, and it is used to transfer data blocks between the
CompactFlash Memory Card data buffer and the host. This register overlaps the Error
Register. The information in Table 3-6 describes the combinations of data register access and
is provided to assist in understanding the overlapped Data Register and Error/Feature Register
rather than attempt to define general PCMCIA word and byte access modes and operations.
Refer to the PCMCIA PC Card Standard Release 2.0 for definitions of the Card Accessing
modes for I/O and memory cycles.
NOTE : Because of the overlapped registers, access to the 1F1, 171 or offset 1
are not defined for word (-CE2 = 0 and -CE1 = 0) operations.
SanDisk products treat these accesses as accesses to the Word Data
Register. The duplicated registers at offsets 8, 9 and Dh have no
restrictions on the operations that can be performed by the socket.
Table 4-6 Data Register
Data Register CE2- CE1- A0 Offset Data Bus
Word Data Register 0 0 X 0,8,9 D15-D0
Even Data Register 1 0 0 0,8 D7-D0
Odd Data Register 1 0 1 9 D7-D0
Odd Data Register 0 1 X 8,9 D15-D0
Error/Feature Register 1 0 1 1,Dh D7-D0
02/07, Rev. 12.0 4-4 © 2007 SanDisk Corporation