SanDisk CompactFlash Extreme III - Manual (Page 52)

ATA Register Set and Protocol SanDisk CompactFlash Card OEM Product Manual
Device Control Register (con’t)
Bit Name Description
D7 X Don’t care.
D6 X Don’t care.
D5 X Don’t care.
D4 X Don’t care.
D3 1 Bit ignored by the card.
D2 SW Rst Set to 1 in order to force the card to perform an AT Disk controller Soft
Reset operation. This does not change the PCMCIA Card Configuration
registers as a hardware reset does. The card remains in Reset until this bit
is reset to “0”.
D1 -IEn Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1,
interrupts from the card are disabled. This bit also controls the Int bit in the
Configuration and Status Register. This bit is set to 0 at power on and
reset.
D0 ERR Bit ignored by the card.
4.5.11 Card (Drive) Address Register (Address–3F7[377]; Offset Fh)
This register is provided for compatibility with the AT disk drive interface. It is recommended
that this register not be mapped into the host's I/O space because of potential conflicts on Bit 7.
The bits are defined as follows:
D7 D6 D5 D4 D3 D2 D1 D0
X -WTG -HS3 -HS2 -HS1 -HS0 -nDS1 -nDS0
02/07, Rev. 12.0 4-8 © 2007 SanDisk Corporation