SanDisk CompactFlash Extreme III - Manual (Page 51)

SanDisk CompactFlash Card OEM Product Manual ATA Register Set and Protocol
4.5.9 Status & Alternate Status Registers (Address–1F7[177]&3F6[376]; Offsets 7 &
Eh)
These registers return the card status when read by the host. Reading the Status Register clears
a pending interrupt while reading the Auxiliary Status Register does not. The meaning of the
status bits are described as follows:
D7 D6 D5 D4 D3 D2 D1 D0
BUSY RDY DWF DSC DRQ CORR 0 ERR
Bit Name Description
D7 BUSY Set when the CompactFlash Card has access to the command buffer and
registers and the host is locked out from accessing the command register
and buffer. No other bits in this register are valid when this bit is set to a 1.
D6 RDY RDY indicates whether the device is capable of performing card operations.
This bit is cleared at power-up and remains cleared until card is ready to
accept a command.
D5 DWF If set, indicates a write fault has occurred.
D4 DSC Set when the card is ready.
D3 DRQ Set when the card requires that information be transferred either to or from
the host through the Data Register.
D2 CORR Set when a correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector read
operation.
D1 0 Always set to 0.
D0 ERR Set when the previous command has ended in some type of error. The bits
in the Error Register contain additional information describing the error.
4.5.10 Device Control Register (Address–3F6[376]; Offset Eh)
This register is used to control the CompactFlash Memory Card interrupt request and to issue
an ATA soft reset to the card. The bits are defined as follows:
D7 D6 D5 D4 D3 D2 D1 D0
X X X X 1 SW Rst -IEn 0
© 2007 SanDisk Corporation 4-7 Rev. 12.0, 02/07