Kawasaki 80C152 - Manual (Page 107)

KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 107 of 120 Ver. 0.9 KS152JB2
PGSRV - Priority bit for GSC Receive Valid interrupt see IPN1.
PGSTE - Priority bit for GSC Transmit Valid interrupt, see IPN1.
PL0 - One of the two bits that determines the Preamble Length, see GMOD.
PL1 - One of the two bits that determines the Preamble Length, see GMOD.
PRBS - (0E4H) - Pseudo-Random Binary Sequence generates the pseudo-random number to be
used in CSMA/CD backoff algorithms.
PS - Priority bit for the LSC service interrupt, see IP.
PT0 - Priority bit for Timer 0 interrupt, see IP.
PT1 - Priority bit for Timer 1 interrupt, see IP.
PX0 - Priority bit for External Interrupt 0, see IP.
PX1 - Priority bit for External interrupt 1, see IP.
RCABT - GSC Receive Abort error bit, see RSTAT.
RDN - GSC Receive Done bit, see RSTAT.
GREN - GSC Receive Enable bit, see RSTAT.
RFNE - GSC Receive FIFO Not Empty bit, see RSTAT.
RI - LSC Receive Interrupt bit, see SCON.
RFIFO - (F4H) - RFIFO is a 3-byte FIFO that contains the receive data from GSC.
RSTAT (0E8H) - Receive Status Register
RSTAT.0 (HABEN) - Hardware Based Acknowledge Enable - If set, enables the hardware based
acknowledge feature.
RSTAT.1 (GREN) - Receiver Enable - When set, the receiver is enabled to accept incoming frames.
The user must clear RFIFO with software before enabling the receiver. RFIFO is cleared by reading
the contents of RFIFO until RFNE = 0. After each read of RFIFO, it takes one machine cycle fir
the status of RFNE to be updated. Setting GREN also clears RDN, CRCE, AE and RCABT. GREN
is cleared by hardware at the end of a reception or if any receive errors are detected. The status of
0 1 2 3 4 5 6 7
CRCE RDN RFNE GREN HABEN AE RCABT OVR