Kawasaki 80C152 User Manual

Page 34

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KS152JB Universal Communications Controller
Technical Specifications

Kawasaki LSI USA, Inc.

Page 34 of 120 Ver. 0.9 KS152JB2

External clock
Internal clock

N

M

N

O

O

N

O

O

O

O

O

N

O

O

O

O

O

O

N

O

O

O

O

O

O

O

O

O

O

O

O

O

Control cpu
Control dma

O

O

O

O

O

1

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

1

O

O

O

O

O

O

O

O

O

O

Raw Receive

1

1

1

1

1

1

1

1

1

N

1

1

1

1

1

1

Raw Transmit

1

1

1

1

1

1

1

1

1

N

1

1

1

1

1

1

CSMA

O

N

N

1

P

1

O

O

M

N

O

O

O

O

O

O

SDLC

N

O

O

P

1

1

O

O

O

O

O

N

O

O

O

O

Table 10:

N-Not available.

M-Mandatory.

O-Optional.

P-Normally Preferred

X-N/A

backoff

preamble

Jam

Clock

contr

ol

r

a

w

tr

a

n

s

m

it

r

a

w

r

e
c
e

i

v

e

c

s

m

a

/

c

d

s

d

l

c

n
o

r

m

a

l

a

lt

e

r

n
a

t

e

d
e

t

e

r

m

i

n

i

s

ti

c

n
o
n
e

8

b

i
t

3
2

b

it

6
4

b

it

d

c

c

r

c

/

e

x

t

e

r

n

a

l

i

n

t

e

r

n

a

l

c

p
u

d

m

a

Manchester (csma/cd)
NRZI (sdlc)
NRZ (ext clock)

O

O

O

N O O

O

O

O

N

M

O

O

O

O

M

N

N

N

N

O O O

O

N

N

N

M

O

O

O

O

N

M

O

O

O

O O O

O

O

O

M

N

O

O

O

O

O

O

Flags:01111110(sdlc)
11/IDLE

N

N

N

O O O

O

N

N

O

O

O

O

O

1

1

P

O

O

O

1

O O

O

O

O

O

O

O

O

O

1

P

1

Table 9:

N-Not available.

M-Mandatory.

O-Optional.

P-Normally Preferred

X-N/A

Data

Flags

CRC

Duplex

Ack

Addr

recognition

m

a
n
c
h

ec

st

er

nr

z

nr

zi

0
1
1
1
1
1
1
0

1

1/
id
le

n
o
n
e

1

6-
bi

t

cc

it

3
2

bi
ta

ut

o

h

al

f

d
u

pl

e
x

fu

ll

d
u

pl

e
x

n
o
n
e

h

ar

d

w
ar

e

us

er

d

ef

n
o
n

e/
al

l

8

bi

t

1
6

bi

t

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