Kawasaki 80C152 - Manual (Page 89)

KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 89 of 120 Ver. 0.9 KS152JB2
If the test for SARn = SBUF is true, and if the flag RI is set, mode_logic (n) returns as 1 and the
remainder of the function is not executed. Otherwise, execution proceeds to then exit if-condition,
testing DARn against SBUF and T1 against 1.
The same considerations regarding SAS and ISA in the SARn test are now applied to DAS and
IDA in the DARn test. If SFR space isn’t selected, no Serial Port buffer is being addressed.
Note that if DMA channel n is configured to Alternate Cycles mode, the logic must examine the
other DCON register, DCONm, to determine if the other channel is also configured to Alternate
Cycles mode and whether its GO bit is set. In the previous figure, the symbol DCONn refers to the
DCON register for “this channel,” and DCONm refers to “the other channel.”
A careful examination of the logic will reveal some idiosyncrasies that the user should be aware
of. First, the logic allows sequential DMA cycles to be generated to service RFIFO, but not to ser-
vice TFIFO. This idiosyncrasy is due to internal timing conflicts, and results in each individual
DMA cycle to TFIFO having to be immediately preceded by an Instruction cycle. The logic disal-
lows that there be two DMAs to TFIFO in a row.
If the user is unaware of this idiosyncrasy, it can cause problems in situations where one DMA
channel is servicing TFIFO and the other is configured to a completely different mode of opera-
tion.
For example, consider the situation where channel 0 is configured to service TFIFO and channel 1
is configured to Alternate Cycles mode. Then DMAs to TFIFO will always override the alternate
cycles of channel 1. If TFIFO needs more than 1 byte it will receive them in precedence over
channel 1, but each DMA to TFIFO must be preceded by an Instruction cycle. The sequence of
cycles might be:
DMA1 cycle
Instruction cycle
DMA 1 cycle, during which TFNF gets set
Instruction cycle
DMA0 cycle
Instruction cycle
DMA0 cycle, as a result of which TFNF gets cleared
Instruction cycle
DMA1 cycle
Instruction cycle
DMA1 cycle
Instruction cycle
......
The requirement that a DMA to TFIFO be preceded by an Instruction cycle can result in the nor-
mal precedence of channel 0 over channel 1 being thwarted. Consider for example the situation
where channel 0 is configured to service TFIFO, and is in the process of doing so, and channel 1