Kawasaki 80C152 - Manual (Page 50)

KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 50 of 120 Ver. 0.9 KS152JB2
number of address bits, but the automatic address recognition feature works on a maximum of 16-
bits.
In SDLC the address are normally unique for each station. However, there are several classes of
messages that are intended for more than one station. These messages are called broadcast and
group addressed frames. An address consisting of all 1s will always be automatically received by
the GSC, this is defined as the broadcast address in SDLC. A group address is an address that is
common to more than one station. The GSC provides address masking bits to provide the capabil-
ity of receiving group address.
If desired, the user software can mask off all the bits of the address. This type of masking puts the
GSC in a pomiscuous mode so that all addresses are received.
CONTROL - The control field is used for initialization of the system, identifying the sequence of
a frame, to identify if the message is complete, to tell secondary stations if a response is expected,
and acknowledgment of previously sent frames. The user software is responsible for insertion of
the control field as the GSC hardware has no provisions for the management of this field. The
interpretation and formation of the control field must also be handled by user software. The infor-
mation following the control field is typically used for information transfer, error reporting, and
various other functions. These functions are accomplished by the format of the control field.
There are three formats available. The types of formats are informational, Supervisory, or Unnum-
bered.
INFO - This is the information field and contains the data that one device on the link wishes to
transmit to another device. It can be of any length the user wishes, but must be a multiple of 8 bits.
It is possible that some frames may contain no information field. The information field is identi-
fied to the receiving stations by the preceding control field and the following CRC. The GSC
determines where the last of the information field is by passing the bits through the CRC genera-
tor. When the last bit or EOF is received the bits that remain constitute the CRC.
CRC -The Cyclic Redundancy Check (CRC) is an error checking sequence commonly used in
serial communications. The C152 offers two types of CRC algorithms, a 16-bit and a 32-bit. The
32-bit algorithm is normally used in CSMA/CD applications and is described in section 3.2.2. In
most SDLC applications a 16-bit CRC is used and the hardware configuration that supports 16-bit
CRC is shown in Figure below The generating polynomial that the CRC generator uses with the
16-bit CRC is:
G(X) = X
16
+ X
12
+ X
5
+ 1
The way the CRC operates is that as a bit is received it is XOR’d with bit 15 of the current CRC
and placed in temporary storage. The result of XOR’ing bit 15 with the received bit is then XOR’d
with bit 4 and bit 11 as the CRC is shifted one position to the right. The bit in temporary storage is
shifted into position 0.
The required CRC length for SDLC is 16 bits. The CRC is automatically stripped from the frame
and not passed on to the CPU. The last 16 bits are then run through the CRC generator to insure