Kawasaki 80C152 - Manual (Page 73)

KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 73 of 120 Ver. 0.9 KS152JB2
data. The receive FIFO is a three byte buffer into which the receive data is loaded. A CPU read of
the FIFO retrieves the oldest data and automatically updates the FIFO pointers. Setting GREN to
a one will clear the receive FIFO. The status of this flag is controlled by the GSC. It is cleared if
user empties receive FIFO.
RSTAT.3 (RDN) - Receive Done - If set, indicates the successful completion of a receiver opera-
tion. Will not be set if a CRC, alignment, abort, or FIFO overrun error occurred. The status of this
flag is controlled by the GSC.
RSTAT.4 (CRCE) - CRC Error - If set, indicates that a properly aligned frame was received with a
mismatched CRC. The status of this flag is controlled by the GSC.
RSTAT.5 (AE) - Alignment Error - In CSMA/CD mode, AE is set if the receiver shift register (an
internal serial-to-parallel converter) is not full and the CRC is bad when an EOF is detected. In
CSMA/CD the EOF is a line idle condition (see LNI) for two bit times. If the CRC is correct
while in CSMA/CD mode, AE is not set and any mis-alignment is assumed to be caused by drib-
ble bits as the line went idle. In SDLC mode, AE is set if a non-byte-aligned flag is received.
CRCE may also be set. The setting of this flag is controlled by the GSC.
RSTAT.5 (AE) - Alignment Error -In CSMA/CD mode, AE is set if the receiver shift register (an
internal serial-to-parallel converter) is not full and the CRC is bad when an EOF is detected. In
CSMA/CD the EOF is a line idle condition (see LNI) for two bit times. If the CRC is correct
while in CSMA/CD mode, AE is not set and any mis-alignment is assumed to be caused by drib-
ble bits as the line went idle. In SDLC mode, AE is set if a non-byte-aligned flag is received.
CRCE may also be set. The setting of this flag is controlled by the GSC.
RSTAT.6 (RCABT) - Receiver Collision/Abort Detect - If set, indicates that a collision was
detected after data had been loaded into the receive FIFO in CSMA/CD mode. In SDLC mode,
RCABT indicates that 7 consecutive ones were detected prior to the end flag but after data has
been loaded into the receive FIFO. AE may also be set. The setting of this flag is controlled by the
GSC.
RSTAT.7 (OVR) - Overrun -If set, indicates that the receive FIFO was full and new shift register
data was written into it. AE and/or CRCE may also be set. The setting of this flag is controlled by
the GSC and it is cleared by user software.
SLOTTM (0BH) - Slot Time -Determines the length of the slot time used in CSMA/CD. A slot
time equals (SLOTTM) X (1/ baud rate). A read of SLOTTM will give the value of the slot time
timer but the value may be invalid as the timer is clocked asynchronously to the CPU. Loading
SLOTTM with 0 results in 256 bit times.