Kawasaki 80C152 - Manual (Page 42)

KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 42 of 120 Ver. 0.9 KS152JB2
Narrow Pulses
A valid Manchester waveform must stay high or low for at least a half bit-time, nominally 4 sam-
ple-times. Jitter tolerance allows a waveform which stays high or low for 3 sample-times to also
be considered valid. A sample sequence which shows a second transition only 1 or 2 sample-times
after the previous transition is considered to be the result of a collision. Thus, sample sequences
such as 0000110000 and 111101111 are interpreted as collisions.
The GSC hardware recognizes the collision to have occurred within 3/8 to 1/2 bit-time following
the second transition.
Missing 0-to-1 Transition
A 0-to-1 transition is expected to occur at the center of any bit cell that begins with 0. If the previ-
ous 1-to-0 transition occurred at the bit cell edge, a jitter tolerance of +1 sample is allowed. Sam-
ple sequences such as 1111:00001111 and 1111:000001111 are valid, where “:” indicates a bit
cell edge. Sequences of the form 1111:000000XXX are interpreted as collisions.
For these kinds of sequences, the GSC recognizes the collision to have occurred within 1 to 11/8
bit-times after the previous 1-to-0 transition.
If the previous 1-to-0 transition occurred at the center of the previous bit cell, a jitter tolerance of
+2 samples is allowed. Thus, sample sequences such as 11110000:00001111 and
111100000:000001111 are valid. Sequences of the form 111100000:000000XXX are interpreted
as collisions.
For these kinds of sequences, the GSC recognizes the collision to have occurred within 1 5/8 to 1
3/4 bit-times after the previous1-to-0 transition.
Unexpected 1-to-0 Transition
If the line is at a logic 1 during the first half of a bit cell, then it is expected to make a 1-to-0 tran-
sition at the midpoint of the bit cell. If the transition is missed, it is assumed that this bit cell is the
first half of an EOF flag (line idle for two bit-times). One bit-time later (which marks the midpoint
of the next bit cell), if there is still no 1-to-0 transition, a valid EOF is assumed and the line idle bit
(LNI in TSTAT) gets set.
However, if the assumed EOF flag is interrupted by a 1-to-0 transition in the bit-time following
the first missing transition, a collision is assumed. In that case the GSC hardware recognizes the
collision to have occurred within 1/2 to 5/8 bit-time after the unexpected transition.