Panasonic MN101C00 - Manual (Page 117)

Chapter 5 Serial Functions
103
When the serial port is enabled
and the SC0CE1 to 0 flags of
the SC0MD0 register are
toggled, the transfer bit count
may change.
The TXD pin goes to a high
level after reception is
complete.
Serial interface 0 begins
operation when the SC0SBOS
or SC0SBIS flag is set to "1."
Set the SC0SBOS or SC0SBIS
flag after all conditions have
been set.
One machine cycle after the
stop bit has been received, the
start condition will no longer be
accepted. Therefore,
consecutive reception must be
performed carefully.
Half-duplex UART Serial Interface
■ Reception
(1) Select UART by setting the SC0CMD flag of the serial interface 0 control
register (SC0CTR) to "1."
(2) Specify the first bit to be transferred (MSB first or LSB first) with the
SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).
(3) Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the
SC0MD0 register.
(4) Select the clock source with the SC0CK1~0 flags of serial interface 0 mode
register 1 (SC0MD1).
(5) Set the SC0CKM flags of the SC0MD1 register to "1" to divide the clock
source frequency by 8.
(6) Set the SC0NPE flag of the serial interface 0 mode register 2 (SC0MD2) to
enable or disable parity.
(7) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the
SC0PM1 to 0 flags of the SC0MD2 register to specify the added parity bit.
(8) Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame
mode.
(9) Select the SC0IOM flag of the SC0MD3 register.
(10) When the SC0IOM flag of the SC0MD3 register is specified that the pin is
independent, set bit 1 of the port 0 direction control register (P0DIR) to the
input mode.
(11) Set bit 0 of the port 0 pull-up resistor control register (P0PLU).
(12) Select serial communication by setting the SC0SBIS flag of the SC0MD3
register to "1."
(13) When the serial transmission begins, the SC0BSY flag of the SC0CTR
register is set to "1," indicating that a serial transfer is in progress.
(14) When the serial transmission is complete, the SC0BSY flag of the SC0CTR
register is cleared to "0" and the SC0 transfer complete interrupt request flag
is set to "1." The SC0TRI flag of the SC0MD1 register is cleared to "1."
Setting the SC0FM flag of the SC0MD2 register to frame
mode automatically sets the SC0LNG2 to 0 flags of the
SC0MD0 register.
After the transfer is complete, the SC0LNG2 to 0 flags of the
SC0MD0 register are automatically set with the transfer bit
count.