NEC V850/SF1 - Manual (Page 26)

CHAPTER 4 CAUTIONS
User’s Manual U15447EJ1V0UM
26
4.5 Bus Interface Pin
The operation of the pin for the bus interface differs between the emulator and the target device as follows.
Table 4-1. Bus Interface Pin Operation List (1/2)
(a) During break
Internal Memory External Memory
Memory Used by
Emulator
Internal
ROM
Internal RAM Internal
Peripheral I/O
Emulation RAM Target System
Pin Name
F R W R R W R W R W R W
A16 to A21 Hold the last accessed address Active Active
AD0 to AD15 Hi-Z Active Active
ASTB H Active Active
R/W H Active Active
DSTB H H Active
LBEN H Active Active
UBEN H Active Active
WAIT Invalid Maskable Maskable
HLDRQ Maskable Maskable Maskable
HLDAK H or L H or L H or L
WRL H H H Note
WRH H H H Note
RD H H Note H
Note Active
Caution When accessing an FCAN register with the external memory expanded, a bus cycle for FCAN
access is generated in AD0 to AD15 and A16 to A21. However, R/W, DSTB, LBEN, UBEN, WRL,
WRH, and RD are inactive.
Remarks 1. F: Fetch
R: Read
W: Write
2. H: High-level output
L: Low-level output
Hi-Z: High-impedance