Document Outline

• NI 6232/6233 User Manual
• Support
  • Worldwide Technical Support and Product Information
  • National Instruments Corporate Headquarters
  • Worldwide Offices
• Important Information
  • Warranty
  • Copyright
  • Trademarks
  • Patents
  • WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
• Compliance
• Contents
• About This Manual
  • Conventions
  • Related Documentation
    • NI-DAQ
    • NI-DAQmx for Linux
    • NI-DAQmx Base
    • LabVIEW
    • LabWindows™/CVI™
    • Measurement Studio
    • ANSI C without NI Application Software
    • .NET Languages without NI Application Software
    • Device Documentation and Specifications
    • Training Courses
    • Technical Support on the Web
• Chapter 1 Getting Started
  • Installing NI-DAQmx
  • Installing Other Software
  • Installing the Hardware
  • Device Pinouts
  • Device Specifications
  • Device Accessories and Cables
• Chapter 2 DAQ System Overview
  • Figure 2-1. Components of a Typical DAQ System
  • DAQ Hardware
    • Figure 2-2. General NI 6232/6233 Block Diagram
    • DAQ-STC2
    • Calibration Circuitry
  • Sensors and Transducers
  • Cables and Accessories
    • Custom Cabling
  • Programming Devices in Software
• Chapter 3 Connector Information
  • I/O Connector Signal Descriptions
    • Table 3-1. I/O Connector Signals
  • RTSI Connector Pinout
• Chapter 4 Analog Input
  • Figure 4-1. NI 6232/6233 Analog Input Circuitry
  • Analog Input Circuitry
  • Analog Input Range
    • Table 4-1. Input Ranges for NI 6232/6233
  • Analog Input Ground-Reference Settings
    • Table 4-2. Analog Input Ground-Reference Settings
    • Figure 4-2. PGIA
    • Table 4-3. Signals Routed to the NI-PGIA
    • Configuring AI Ground-Reference Settings in Software
    • Figure 4-3. Enabling Multimode Scanning in LabVIEW
  • Multichannel Scanning Considerations
    • Use Low Impedance Sources
    • Use Short High-Quality Cabling
    • Carefully Choose the Channel Scanning Order
      • Avoid Switching from a Large to a Small Input Range
      • Insert Grounded Channel between Signal Channels
      • Minimize Voltage Step between Adjacent Channels
    • Avoid Scanning Faster Than Necessary
      • Example 1
      • Example 2
  • Analog Input Data Acquisition Methods
    • Software-Timed Acquisitions
    • Hardware-Timed Acquisitions
      • Buffered
      • Non-Buffered
  • Analog Input Triggering
  • Connecting Analog Voltage Input Signals
    • Table 4-4. Analog Input Configuration
  • Types of Signal Sources
    • Floating Signal Sources
    • Ground-Referenced Signal Sources
    • Differential Connection Considerations
    • Differential Connections for Ground-Referenced Signal Sources
      • Figure 4-4. Differential Connections for Ground-Referenced Signal Sources
      • Differential Input Biasing
    • Differential Connections for Non-Referenced or Floating Signal Sources
      • Figure 4-5. Differential Connections for Floating Signal Sources
    • Single-Ended Connection Considerations
      • Single-Ended Connections for Floating or Grounded Signal Sources
      • Figure 4-6. Single-Ended Connections for Floating Signal Sources (RSE Configuration)
  • Field Wiring Considerations
  • Analog Input Timing Signals
    • Figure 4-7. Analog Input Timing Options
    • Figure 4-8. Interval Sampling
    • Figure 4-9. Posttriggered Data Acquisition Example
    • Figure 4-10. Pretriggered Data Acquisition Example
    • AI Sample Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Routing AI Sample Clock Signal to an Output Terminal
      • Other Timing Requirements
      • Figure 4-11. ai/SampleClock and ai/StartTrigger
    • AI Sample Clock Timebase Signal
    • AI Convert Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Routing AI Convert Clock Signal to an Output Terminal
      • Using a Delay from Sample Clock to Convert Clock
      • Figure 4-12. ai/SampleClock and ai/ConvertClock
      • Other Timing Requirements
      • Figure 4-13. Single External Signal Driving ai/SampleClock and ai/ConvertClock Simultaneously
    • AI Convert Clock Timebase Signal
    • AI Hold Complete Event Signal
    • AI Start Trigger Signal
      • Using a Digital Source
      • Routing AI Start Trigger to an Output Terminal
    • AI Reference Trigger Signal
      • Figure 4-14. Reference Trigger Final Buffer
      • Using a Digital Source
      • Routing AI Reference Trigger Signal to an Output Terminal
    • AI Pause Trigger Signal
      • Using a Digital Source
      • Routing AI Pause Trigger Signal to an Output Terminal
  • Getting Started with AI Applications in Software
• Chapter 5 Analog Output
  • Figure 5-1. NI 6232/6233 Analog Output Circuitry
  • Analog Output Circuitry
  • Minimizing Glitches on the Output Signal
  • Analog Output Data Generation Methods
    • Software-Timed Generations
    • Hardware-Timed Generations
      • Non-Buffered
      • Buffered
  • Analog Output Triggering
  • Connecting Analog Voltage Output Signals
    • Figure 5-2. Analog Output Connections
  • Analog Output Timing Signals
    • Figure 5-3. Analog Output Timing Options
    • AO Start Trigger Signal
      • Using a Digital Source
      • Routing AO Start Trigger Signal to an Output Terminal
    • AO Pause Trigger Signal
      • Figure 5-4. ao/PauseTrigger with the Onboard Clock Source
      • Figure 5-5. ao/PauseTrigger with Other Signal Source
      • Using a Digital Source
      • Routing AO Pause Trigger Signal to an Output Terminal
    • AO Sample Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Routing AO Sample Clock Signal to an Output Terminal
      • Other Timing Requirements
      • Figure 5-6. ao/SampleClock and ao/StartTrigger
    • AO Sample Clock Timebase Signal
  • Getting Started with AO Applications in Software
• Chapter 6 Digital Input and Output
  • I/O Protection
  • Programmable Power-Up States
  • Connecting Digital I/O Signals
    • Figure 6-1. NI 6232 Digital I/O Connections (DO Source)
    • Figure 6-2. NI 6233 Digital I/O Connections (DO Sink)
  • Logic Conventions
    • Table 6-1. NI 6232/6233 Logic Conventions
  • Getting Started with DIO Applications in Software
• Chapter 7 Counters
  • Figure 7-1. M Series Counters
  • Counter Input Applications
    • Counting Edges
      • Single Point (On-Demand) Edge Counting
      • Figure 7-2. Single Point (On-Demand) Edge Counting
      • Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger
      • Buffered (Sample Clock) Edge Counting
      • Figure 7-4. Buffered (Sample Clock) Edge Counting
      • Non-Cumulative Buffered Edge Counting
      • Figure 7-5. Non-Cumulative Buffered Edge Counting
      • Controlling the Direction of Counting
    • Pulse-Width Measurement
      • Single Pulse-Width Measurement
      • Figure 7-6. Single Pulse-Width Measurement
      • Buffered Pulse-Width Measurement
      • Figure 7-7. Buffered Pulse-Width Measurement
    • Period Measurement
      • Single Period Measurement
      • Figure 7-8. Single Period Measurement
      • Buffered Period Measurement
      • Figure 7-9. Buffered Period Measurement
    • Semi-Period Measurement
      • Single Semi-Period Measurement
      • Buffered Semi-Period Measurement
      • Figure 7-10. Buffered Semi-Period Measurement
    • Frequency Measurement
      • Method 1-Measure Low Frequency with One Counter
      • Figure 7-11. Method 1
      • Method 1b-Measure Low Frequency with One Counter (Averaged)
      • Figure 7-12. Method 1b
      • Method 2-Measure High Frequency with Two Counters
      • Figure 7-13. Method 2
      • Method 3-Measure Large Range of Frequencies Using Two Counters
      • Figure 7-14. Method 3
      • Choosing a Method for Measuring Frequency
      • Table 7-1. Frequency Measurement Method 1
      • Table 7-2. Frequency Measurement Method Comparison
    • Position Measurement
      • Measurements Using Quadrature Encoders
      • Figure 7-15. X1 Encoding
      • Figure 7-16. X2 Encoding
      • Figure 7-17. X4 Encoding
      • Figure 7-18. Channel Z Reload with X4 Decoding
      • Measurements Using Two Pulse Encoders
      • Figure 7-19. Measurements Using Two Pulse Encoders
    • Two-Signal Edge-Separation Measurement
      • Single Two-Signal Edge-Separation Measurement
      • Figure 7-20. Single Two-Signal Edge-Separation Measurement
      • Buffered Two-Signal Edge-Separation Measurement
      • Figure 7-21. Buffered Two-Signal Edge-Separation Measurement
  • Counter Output Applications
    • Simple Pulse Generation
      • Single Pulse Generation
      • Figure 7-22. Single Pulse Generation
      • Single Pulse Generation with Start Trigger
      • Figure 7-23. Single Pulse Generation with Start Trigger
      • Retriggerable Single Pulse Generation
      • Figure 7-24. Retriggerable Single Pulse Generation
    • Pulse Train Generation
      • Continuous Pulse Train Generation
      • Figure 7-25. Continuous Pulse Train Generation
    • Frequency Generation
      • Using the Frequency Generator
      • Figure 7-26. Frequency Generator Block Diagram
      • Figure 7-27. Frequency Generator Output Waveform
    • Frequency Division
    • Pulse Generation for ETS
      • Figure 7-28. Pulse Generation for ETS
  • Counter Timing Signals
    • Counter n Source Signal
      • Table 7-3. Counter Applications and Counter n Source
      • Routing a Signal to Counter n Source
      • Routing Counter n Source to an Output Terminal
    • Counter n Gate Signal
      • Routing a Signal to Counter n Gate
      • Routing Counter n Gate to an Output Terminal
    • Counter n Aux Signal
      • Routing a Signal to Counter n Aux
    • Counter n A, Counter n B, and Counter n Z Signals
      • Routing Signals to A, B, and Z Counter Inputs
      • Routing Counter n Z Signal to an Output Terminal
    • Counter n Up_Down Signal
    • Counter n HW Arm Signal
      • Routing Signals to Counter n HW Arm Input
    • Counter n Internal Output and Counter n TC Signals
      • Routing Counter n Internal Output to an Output Terminal
    • Frequency Output Signal
      • Routing Frequency Output to a Terminal
  • Default Counter Terminals
    • Table 7-4. NI 6232/6233 Device Default NI-DAQmx Counter/Timer Pins
  • Counter Triggering
    • Arm Start Trigger
    • Start Trigger
    • Pause Trigger
  • Other Counter Features
    • Cascading Counters
    • Counter Filters
      • Table 7-5. Filters
      • Figure 7-29. Filter Example
    • Prescaling
      • Figure 7-30. Prescaling
    • Duplicate Count Prevention
      • Duplicate Count Prevention Example
      • Figure 7-31. Duplicate Count Prevention Example
      • Duplicate Count Example
      • Figure 7-32. Duplicate Count Example
      • Example Application That Prevents Duplicate Count
      • Figure 7-33. Duplicate Count Prevention Example
      • When To Use Duplicate Count Prevention
      • Enabling Duplicate Count Prevention in NI-DAQmx
    • Synchronization Modes
      • Table 7-6. Synchronization Mode Conditions
      • 80 MHz Source Mode
      • Figure 7-34. 80 MHz Source Mode
      • Other Internal Source Mode
      • Figure 7-35. Other Internal Source Mode
      • External Source Mode
      • Figure 7-36. External Source Mode
• Chapter 8 PFI
  • Figure 8-1. NI 6232/6233 PFI Input Circuitry
  • Figure 8-2. NI 6232/6233 PFI Output Circuitry
  • Using PFI Terminals as Timing Input Signals
  • Exporting Timing Output Signals Using PFI Terminals
  • Using PFI Terminals as Static Digital Inputs and Outputs
  • Connecting PFI Input Signals
    • Figure 8-3. PFI Input Signals Connections
  • PFI Filters
    • Table 8-1. Filters
    • Figure 8-4. Filter Example
  • I/O Protection
  • Programmable Power-Up States
  • Connecting Digital I/O Signals
    • Figure 8-5. NI 6232 Digital I/O Connections (DO Source)
    • Figure 8-6. NI 6233 Digital I/O Connections (DO Sink)
• Chapter 9 Isolation and Digital Isolators
  • Table 9-1. Ground Symbols
  • Figure 9-1. General NI 6232/6233 Block Diagram
  • Digital Isolation
  • Benefits of an Isolated DAQ Device
• Chapter 10 Digital Routing and Clock Generation
  • Clock Routing
    • Figure 10-1. M Series Clock Routing Circuitry
    • 80 MHz Timebase
    • 20 MHz Timebase
    • 100 kHz Timebase
    • External Reference Clock
    • 10 MHz Reference Clock
  • Synchronizing Multiple Devices
  • Real-Time System Integration Bus (RTSI)
    • RTSI Connector Pinout
      • Figure 10-2. NI 6232/6233 RTSI Pinout
      • Table 10-1. RTSI Signal Descriptions
    • Using RTSI as Outputs
    • Using RTSI Terminals as Timing Input Signals
    • RTSI Filters
      • Table 10-2. Filters
      • Figure 10-3. Filter Example
  • PXI Clock and Trigger Signals
    • PXI_CLK10
    • PXI Triggers
    • PXI_STAR Trigger
    • PXI_STAR Filters
      • Table 10-3. Filters
      • Figure 10-4. Filter Example
• Chapter 11 Bus Interface
  • DMA Controllers
  • PXI Considerations
    • PXI Clock and Trigger Signals
    • PXI and PXI Express
    • Using PXI with CompactPCI
  • Data Transfer Methods
    • Direct Memory Access (DMA)
    • Interrupt Request (IRQ)
    • Programmed I/O
    • Changing Data Transfer Methods between DMA and IRQ
• Chapter 12 Triggering
  • Triggering with a Digital Source
    • Figure 12-1. Falling-Edge Trigger
• Appendix A Device-Specific Information
  • Figure A-1. NI 6232 Pinout
  • Table A-1. NI 6232 Device Default NI-DAQmx Counter/Timer Pins
  • Figure A-2. NI 6233 Pinout
  • Table A-2. NI 6233 Device Default NI-DAQmx Counter/Timer Pins
• Appendix B Troubleshooting
  • Figure B-1. ai/SampleClock and ai/ConvertClock
• Appendix C Technical Support and Professional Services
• Glossary
  • Numbers/Symbols
  • A
  • B-C
  • D
  • E
  • F
  • G-I
  • K-M
  • N
  • O-P
  • Q
  • R-S
  • T
  • U-V
  • W
• Index
  • Symbols
  • Numerics
  • A
  • B-C
  • D
  • E
  • F-I
  • K-N
  • O-R
  • S
  • T-U
  • V-X