National Instruments NI PXIe-6672 - Manual (Page 32)

Chapter 3 Hardware Overview
© National Instruments Corporation 3-19 NI PXIe-6672 User Manual
destinations with significantly different propagation delays. By delaying
the pulse on the routes with shorter paths, you can compensate for the
propagation delay. An example of such a situation would be when a trigger
pulse must arrive nearly simultaneously at the local backplane and the
backplane of another chassis separated by 50 m of coaxial cable.
Using the PXI_CLK10 PLL
A module in System Timing Slot of a PXI Express chassis can replace the
PXI_CLK10 reference clock. The NI PXIe-6672 offers three options for
this replacement. This section describes each option.
• The first option is to replace PXI_CLK10 directly with the TCXO
output on the NI PXIe-6672. This oscillator is a more stable and
accurate reference than the native backplane clock.
• The second option is to route a 10 MHz clock directly from CLKIN on
the front panel to PXI_CLK10_IN, which is the pin on the backplane
that will replace PXI_CLK10. There is a delay through the module, as
well as a distribution delay on the backplane. These delays tend to
be similar for chassis of the same model, so routing the same clock
to a pair of chassis usually matches PXI_CLK10 to within a few
nanoseconds.
• The third option is to employ the NI PXIe-6672 PLL circuitry for the
TCXO. As in option 1, the output of the TCXO replaces the native
10 MHz signal. However, this scheme also requires an input signal
on CLKIN. This signal must be a stable clock, and its frequency must
be a multiple of 1 MHz (5 MHz or 13 MHz, for example) between
1 MHz and 105 MHz. The PLL feedback circuit generates a voltage
proportional to the phase difference between the reference input on
PXI_CLK10 and the output of the TCXO. This PLL voltage output
then tunes the output frequency of the TCXO. As long as the incoming
signal is a stable 1 MHz frequency multiple, the PLL circuit quickly
locks the TCXO to the reference, eliminating all phase drift between
the two signals.
Using the PLL provides several advantages over the other two options for
replacing the PXI backplane clock:
• CLKIN is not required to be 10 MHz. If you have a stable reference
that is a multiple of 1 MHz, such as 13 or 5 MHz, you can
frequency-lock the chassis to it.
• If CLKIN stops or becomes disconnected, PXI_CLK10 is still present
in the chassis.