Texas Instruments TMS320C6455 - Manual (Page 28)

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2.9 Self-Refresh Mode
Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2
memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the
DDR2 SDRAM maintains valid data while consuming a minimal amount of power. When the SR bit is
asserted, the DDR2 memory controller continues normal operation until all outstanding memory access
requests have been serviced and the refresh backlog has been cleared. At this point, all open pages of
DDR2 SDRAM are closed and a self-refresh (SLFRFR) command (an autorefresh command with
DSDCKE low) is issued.
The DDR2 memory controller exits the self-refresh state when a memory access is received or when the
SR bit in SDRFC is cleared. While in the self-refresh state, if a request for a memory access is received,
the DDR2 memory controller services the memory access request, returning to the self-refresh state upon
completion.
The DDR2 memory controller will not exit the self-refresh state (whether from a memory access request or
from clearing the SR bit) until T_CKE + 1 cycles have expired since the self-refresh command was issued.
The value of T_CKE is defined in the SDRAM timing 2 register (SDTIM2).
After exiting from the self-refresh state, the DDR2 memory controller will not immediately start using
commands. Instead, it will wait T_XSNR+1 clock cycles before issuing non-read commands and
T_XSRD+1 clock cycles before issuing read commands. The SDRAM timing 2 register (SDTIM2)
programs the values of T_XSNR+1 and T_XSRD+1.
2.10 Reset Considerations
The DDR2 memory controller can be reset through a hard reset or a soft reset. A hard reset resets the
state machine, the FIFOs, and the internal registers. A soft reset only resets the state machine and the
FIFOs. A soft reset does not reset the internal registers except for the interrupt registers. Register
accesses cannot be performed while either reset is asserted.
The DDR2 memory controller hard and soft reset are derived from device-level resets. C6455/C6454
devices have several types of device-level resets: power-on reset, warm reset, max reset, system reset,
and CPU reset.
Table 8 shows the relationship between the device-level resets and the DDR2 memory
controller resets.
Table 8. Device and DDR2 Memory Controller Reset Relationship
DDR2 Memory
Controller Reset
Effect Initiated by:
Hard reset Resets control logic and all DDR2 memory Power on reset
controller registers Warm reset
Max reset
Soft reset Resets control logic and interrupt registers System reset
CPU reset
In case of a warm reset on the DSP, the DDR2 SDRAM memory content can be retained if the user
places the DDR2 SDRAM in self-refresh mode before invoking the warm reset. However, the DDR2
memory controller registers will be reset and need to be reprogrammed to the required values after the
warm reset. For more information on the device-level resets, see the device-specific data manual.
2.11 DDR2 SDRAM Memory Initialization
DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation
for the device. These registers control parameters such as burst type, burst length, and CAS latency. The
DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by
issuing MRS and EMRS commands during the initialization sequence described in
Section 2.11.2 and
Section 2.11.3 . The initialization sequence performed by the DDR2 memory controller is compliant with
the JESDEC79-2A specification.
The DDR2 memory controller performs the initialization sequence under the following conditions:
• Automatically following a hard or soft reset, see Section 2.11.2 .
28 C6455/C6454 DDR2 Memory Controller SPRU970G – December 2005 – Revised June 2011
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