Figure 28 – Xilinx ML403 User Manual
Page 25
Simulation
XAPP979 (v1.0) February 26, 2007
25
R
In most cases, after data is transmitted, the test waits for an interrupt from the OPB IIC.
Internal signal names used in the OPB IIC core are provided in
Table 6
.
Figure 28: OPB IIC Simulation
Table 6: Internal Signals in OPB IIC
Signal Name
Functionality
Txak
Transmit acknowledge
Gc_en
General call address enbale
Ro_prev
Receive overrun prevent
Dtre
Data transmit register empty
Msms
Master/Slave select
Dtr(7:0)
Data Transmit Register
Adr(7:0)
IIC Slave Address Register
Ten_adr(7:5)
10-bit Slave Address Register
Bb
Bus Busy
Aas
Addressed as slave
Al
Arbitration lost
Srw
Slave read/write
Abgc
Addressed by general call
Data_iic(7:0)
IIC data for microprocessor
New_rcv_data
New data received on IIC bus
Tx_under_prev
Transmit FIFO Empty IRQs
slave_sda
SDA value when slave
master_sda
SDA value when master
sm_stop
Stop condition needs to be generated
rsta_tx_under_prev
Repeated start Tx underflow prevent
BFM
IIC_20
B
as
e Addre
ss
0xE0000000
B
as
e Addre
ss
0xE1000000
IIC_AA
X979_2
8
_012907
S
CL
S
DA