Xilinx ML403 User Manual
Page 30
Simulation
XAPP979 (v1.0) February 26, 2007
30
R
provides the test code used in the simulation with the OPB IIC with the AA address
as the master.
Figure 33: Test code with iic_AA as Master
write CR_20 0x40 -- GC, En
write ADR_20 0x20 -
S
et
s
a
ddre
ss
as
0x20
write CR_AA 0x01 - En
ab
le
write ADR_AA 0xAA
write RC_FIFO_PIRQ_AA 0x0
write IER_AA 0x04 -- En
ab
le DTRE interr
u
pt
write RC_FIFO_PIRQ 0x01 (47
3
us
)
write DTR_20 0x
3
C
write DTR_20 0x55
write DTR_AA 0x0 -- Gener
a
l C
a
ll
write CR_AA 0x0D -- R
S
TA, TxAK, TX, M
S
M
S
, En
ab
le
w
a
it_for_intr
re
a
d
S
R_AA 0xC4 -- TFE, RFE, BB
re
a
d I
S
R_AA 0xD4 -- TFHE, DTRE
write CR_AA 0x
3
5 R
S
TA, M
S
, EN (547
us
)
write DTR_AA 0x21
write DTR_AA 0xFF
write IER_AA 0x0
8
w
a
it_for_intr -- w
a
iting for DRR_AA f
u
ll
re
a
d
S
R_AA 0x0C --
S
RW, BB (67
8
us
)
write CR_AA 0x
3
7 -- Cle
a
r FIFO
write CR_AA 0x
3
5
re
a
d DRR_AA 0x
3
C
write I
S
R_AA 0xC
*
write DTR_AA 0x21
w
a
it_for_intr
re
a
d
S
R_AA 0x
8
C
re
a
d I
S
R_AA 0xCA -- TXER, DFF F
u
ll
write CR_AA 0x41
re
a
d DRR_AA 0x55 (7
8
7
us
)
write I
S
R_AA 0xC
8
write IRE_AA 0x10 -- En
ab
le B
us
i
s
not B
us
y
w
a
it_for_intr
X979_
33
_012907