Xilinx ML403 User Manual
Page 3
Introduction
XAPP979 (v1.0) February 26, 2007
3
R
shows the format of the data transfer of two bytes on the IIC bus, beginning with the
START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus.
After a START condition, an eight bit field is transmitted containing a 7 bit address and a single
Read/Write (R/W) bit. This 8 bit address/direction field is followed by an Acknowledge bit. After
the address/data field, an eight bit data field is followed by an acknowledge bit (A). The last 8-
bit data field is followed by a not acknowledge bit (A). This is followed by the STOP condition
(P).
A single message can contain multiple start conditions, or a repeated start, without intervening
STOP conditions.
In this data transfer, there are two acknowledge bits and one Not Acknowledge on the IIC bus.
The distinction between a Not Acknowledge and a No Acknowledge is that Not Acknowledge
occurs after a master has read a byte from a slave and a No Acknowledge occurs after a master
has written a byte to a slave.
A synchronized SCL is generated with its LOW period determined by the device with the
longest low period and its HIGH period determined by the device with the shortest HIGH
period.
shows the data transfer on the IIC bus, beginning with the START condition and
ending with the STOP condition.
Figure 4: Data Transfer on the IIC Bus
Figure 5: Generic Data Transer on the IIC Bus
S
DA
S
l
a
ve
Addre
ss
F
A
A
R/W
S
P
F
S
CL
X979_04_012907
D
a
t
a
D
a
t
a
A
1
2
1
2
7
8
9
3
-
8
9
Acknowledgment
s
ign
a
l from
s
l
a
ve
Acknowledgment
s
ign
a
l from receiver
Byte complete;
interr
u
pt within
s
l
a
ve
Clock line
s
held low while
interr
u
pt
s
a
re
s
erviced
S
or
S
R
S
r
or
P
P
S
r
X979_05_022
3
07
S
TART or
repe
a
ted
S
TART
condition
S
TOP or
repe
a
ted
S
TART
condition
M
S
B
S
CL
S
DA
ACK
ACK