Rainbow Electronics MAX6871 - Manual (Page 34)

MAX6870/MAX6871
EEPROM-Programmable Hex/Quad
Power-Supply Sequencers/Supervisors with ADC
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and the master device at clock rates up to 400kHz. Figure
2 shows the interface timing diagram. The
MAX6870/MAX6871 are transmit/receive slave-only
devices, relying upon a master device to generate a
clock signal. The master device (typically a microcon-
troller) initiates data transfer on the bus and generates
SCL to permit that transfer.
A master device communicates to the MAX6870/
MAX6871 by transmitting the proper address followed by
command and/or data words. Each transmit sequence is
framed by a START (S) or REPEATED START (SR) condi-
tion and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge pulse.
SCL is a logic input, while SDA is a logic input/open-
drain output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7k Ω
for most applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 3),
otherwise the MAX6870/MAX6871 register a START or
STOP condition (Figure 4) from the master. SDA and
SCL idle high when the bus is not busy.
Start and Stop Conditions
Both SCL and SDA idle high when the bus is not busy. A
master device signals the beginning of a transmission
with a START (S) condition (Figure 4) by transitioning
SDA from high to low while SCL is high. The master
device issues a STOP (P) condition (Figure 4) by transi-
tioning SDA from low to high while SCL is high. A STOP
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
t
HIGH
t LOW
t R
t F
t SU:DAT
t SU:STA
t SU:STO t HD:STA
t
BUF
t HD:STA
t HD:DAT
SCL
SDA
START
CONDITION
Figure 2. Serial-Interface Timing Details
DATA LINE STABLE,
DATA VALID
SDA
SCL
CHANGE OF
DATA ALLOWED
Figure 3. Bit Transfer
P S
START
CONDITION
SDA
SCL
STOP
CONDITION
Figure 4. Start and Stop Conditions