Rainbow Electronics MAX6871 - Manual (Page 43)

MAX6870/MAX6871
EEPROM-Programmable Hex/Quad
Power-Supply Sequencers/Supervisors with ADC
______________________________________________________________________________________ 43
Configuring the Watchdog Timers
(Registers 3Ch–3Fh)
A watchdog timer monitors microprocessor (µP) soft-
ware execution for a stalled condition and resets the µP
if it stalls. The output of a watchdog timer (one of the
programmable outputs) connects to the reset input or a
nonmaskable interrupt of the µP.
Registers 3Ch–3Fh configure the watchdog functionality
of the MAX6870/MAX6871. Program each watchdog
timer to assert one or more programmable outputs (see
Tables 10–21). Program each watchdog timer to reset on
one of the GPI_ inputs, one of the programmable out-
puts, or a combination of one GPI_ input and one pro-
grammable output.
Each watchdog timer features independent initial and
normal watchdog timeout periods. The initial watchdog
timeout period applies immediately after power-up, after a
reset event takes place, or after enabling the watchdog
timer. The initial watchdog timeout period allows the µP to
perform its initialization process. If no pulse occurs during
the initial watchdog timeout period, the µP is taking too
long to initialize, indicating a potential problem.
The normal watchdog timeout period applies in every
other cycle after the initial watchdog timeout period
occurs. The normal watchdog timeout period monitors
a pulsed output of the µP that indicates when normal
processor behavior occurs. If no pulse occurs during
the normal watchdog timeout period, this indicates that
the processor has stopped operating or is stuck in an
infinite execution loop.
Disable or enable each initial timeout period through reg-
isters 3Ch and 3Eh. Registers 3Dh and 3Fh program the
initial and normal watchdog timeout periods, and enable
or disable each watchdog timer. See Tables 27 and 28
for a summary of the watchdog behavior.
Fault Detector
Registers 60h–62h store all fault conditions, including
undervoltage, overvoltage, GPI_, and watchdog timer
faults (see Table 29). Fault registers are read-only and
lose contents upon power removal. The first read com-
mand from the fault registers after power-up gives invalid
data. Any MR assertion writes to the fault register.
Reading the fault register clears all fault flags. Both GPI_
Table 27. Watchdog Inputs (Addresses
3Ch (Watchdog 1), 3Eh (Watchdog 2))
BIT N A M E DESCRIPTION
[1:0]
Watchd og
Inp ut
S el ecti on
00 = GPI1 input
01 = GPI2 input
10 = GPI3 input
11 = GPI4 input
[4:2]
Watchd og
Inter nal
Inp ut
S el ecti on
000 = P O1 ( M AX 6870) , not used ( M AX 6871)
001 = P O2 ( M AX 6870) , not used ( M AX 6871)
010 = P O3 ( M AX 6870) , P O1 ( M AX 6871)
011 = P O4 ( M AX 6870) , P O2 ( M AX 6871)
100 = P O5 ( M AX 6870) , P O3 ( M AX 6871)
101 = P O6 ( M AX 6870) , P O4 ( M AX 6871)
110 = P O7 ( M AX 6870) , P O5 ( M AX 6871)
111 = P O8 ( M AX 6870) , not used ( M AX 6871)
[6:5]
Watchd og
D ep end ency
on Inp uts
00 = 11 = watchdog clear depends on
both GPI_ from 3Ch[1:0] and PO_ from
3Ch[4:2].
01 = watchdog clear depends only on
PO_ from 3Ch[4:2].
10 = watchdog clear depends only on
GPI_ from 3Ch[1:0].
[7]
Ini ti al
Watchd og
Ti m eout
E nab l e
0 = disables initial watchdog timeout
period (normal watchdog timeout not
affected).
1 = enables initial watchdog timeout
period.
Table 28. Watchdog Timeout Period
Selection (Addresses 3Dh (Watchdog 1),
3Fh (Watchdog 2))
BIT NAME DESCRIPTION
[2:0]
Normal
Watchdog
Timeout Period
000 = 6.25ms
001 = 25ms
010 = 100ms
011 = 400ms
100 = 1.6s
101 = 6.4s
110 = 25.6s
111 = 102.4s
[5:3]
Initial Watchdog
Timeout Period
(Immediately
following power-
up, reset event,
or enabling
watchdog)
000 = 6.25ms
001 = 25ms
010 = 100ms
011 = 400ms
100 = 1.6s
101 = 6.4s
110 = 25.6s
111 = 102.4s
[6]
Watchdog
Enable
0 = disables watchdog timer
1 = enables watchdog timer
[7] — Not used