Rainbow Electronics MAX17036 - Manual (Page 12)

MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
12 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 CSN3
Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
2 CSP3
Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the
output inductor is utilized for current sensing.
To disable phase 3, connect CSP3 to V
CC and CSN3 to GND.
3 THRM
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V CC
and GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of
V
CC ) at the desired high temperature.
4 IMON
Current Monitor Output Pin. The output current at this pin is:
I IMON = G M(IMON) x V(CSP_,CSN_)
where G M(IMON) = 1.6mS typical and  denotes summation over all enabled phases.
An external resistor R IMON between IMON and GNDS sets the current-monitor output voltage:
V IMON = I LOAD x R SENSE x G M(IMON) x R IMON
where R SENSE is the value of the effective current-sense resistance.
Choose R IMON such that V IMON does not exceed 900mV at the maximum expected load current I MAX .
IMON is high impedance when the MAX17030/MAX17036 are in shutdown.
5 ILIM
Current-Limit Adjust Input. The valley positive current-limit threshold voltages at V(CSP_,CSN_) are
precisely 1/10 the differential voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The
valley negative current-limit thresholds are typically -125% of the corresponding valley positive
current-limit thresholds. Connect ILIM to V
CC to get the default current-limit threshold setting of
22.5mV typ.
6 TIME
Slew-Rate Adjustment Pin. The total resistance R TIME from TIME to GND sets the internal slew rate:
Slew rate = (12.5mV/µs) x (71.5k
/R TIME )
where R TIME is between 35.7k
and 178k
.
This “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes
and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is
always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions
is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew
rate defined above.
7 V CC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
8 FB
Feedback Voltage Input. The voltage at the FB pin is compared with the slew-rate-controlled target
voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator
(slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum
of the inductor currents is essential for cycle-by-cycle stability.
The external connections and compensation at FB depend on the desired DC and transient (AC)
droop values. If DC droop = AC droop, then short FB to FBAC. To disable DC droop, connect FB to the
remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through
capacitor C, where the R x C time constant should be at least 3x the switching period per phase.