Rainbow Electronics MAX17036 - Manual (Page 37)

MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
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where:
where R
SENSE
is the sensing resistor or effective induc-
tor DCR.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the out-
put capacitance and processor’s power-dissipation
requirements. The MAX17030/MAX17036 use a
transconductance amplifier to set the transient and DC
output voltage droop (Figure 3) as a function of the
load. This adjustability allows flexibility in the selected
current-sense resistor value or inductor DCR, and
allows smaller current-sense resistance to be used,
reducing the overall power dissipated.
Steady-State Voltage Positioning
Connect a resistor (R FB ) between FB and V OUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (R
DROOP
):
where the effective current-sense resistance (R SENSE )
depends on the current-sense method (see the Current
Sense section), and the voltage positioning amplifier’s
transconductance (G m(FB) ) is typically 400µS as
defined in the Electrical Characteristics table. The con-
troller sums together the input signals of the current-
sense inputs (CSP_, CSN_).
When the inductors’ DCR is used as the current-sense
element (R
SENSE = R DCR ), each current-sense input
should include an NTC thermistor to minimize the tem-
perature dependence of the voltage-positioning slope.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Refer to the MAX17030 Evaluation Kit specifi-
cation for a layout example and follow these guidelines
for good PCB layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
2) Connect all analog grounds to a separate solid cop-
per plane, which connects to the ground pin of the
Quick-PWM controller. This includes the V
CC
bypass
capacitor, FB, and GNDS bypass capacitors.
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCB (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single m
Ω
of excess trace resistance causes a measurable
efficiency penalty.
4) Keep the high current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
5) CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin
sense connections to guarantee the current-sense
accuracy.
6) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
7) Route high-speed switching nodes away from sen-
sitive analog areas (FB, CSP_, CSN_, etc.).
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C IN ,
C OUT , and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50mils to 100mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST diodes and
capacitors, V DD bypass capacitor) together near
the controller IC.
R
R
R G
FB
DROOP
SENSE m FB
=
( )
I
V
R
VALLEY
LIMIT
SENSE
=