Rainbow Electronics MAX17036 User Manual
Page 29
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
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PSI Transitions
When PSI is pulled low, the MAX17030/MAX17036
immediately disable phase 3 (PWM3 three-state,
DRSKP forced low) and enter 2-phase PWM operation
(see Figure 7). When PSI is pulled high, the MAX17030/
MAX17036 enable phase 3.
Forced-PWM Operation (Normal Mode)
During soft-shutdown and normal operation—when the
CPU is actively running (DPRSLPVR = low, Table 5)—
the MAX17030/MAX17036 operate with the low-noise,
forced-PWM control scheme. Forced-PWM operation
disables the zero-crossing comparators of all active
phases, forcing the low-side gate-drive waveforms to
constantly be the complement of the high-side gate-
drive waveforms. This keeps the switching frequency
constant and allows the inductor current to reverse
under light loads, providing fast, accurate negative out-
put-voltage transitions by quickly discharging the output
capacitors.
Forced-PWM operation comes at a cost: the no-load
+5V bias supply current remains between 10mA to
50mA per phase, depending on the external MOSFETs
and switching frequency. To maintain high efficiency
under light-load conditions, the processor can switch
the controller to a low-power pulse-skipping control
scheme by entering suspend mode.
PSI determines how many phases are active when oper-
ating in forced-PWM mode (DPRSLPVR = low). When PSI
is pulled low, phases 1 and 2 remain active but phase 3
is disabled (PWM3 three-state, DRSKP forced low).
Light-Load Pulse-Skipping Operation
(Deeper Sleep)
During soft-start and normal operation when
DPRSLPVR is pulled high, the MAX17030/MAX17036
operate with a single-phase pulse-skipping mode. The
pulse-skipping mode enables the driver’s zero-crossing
comparator, so the controller pulls DL1 low when its cur-
rent-sense inputs detect “zero” inductor current. This
keeps the inductor from discharging the output capaci-
tors and forces the controller to skip pulses under light-
load conditions to avoid overcharging the output.
CPU FREQ
CPU LOAD
CPU CORE
VOLTAGE
VID (D0–D6)
PWRGD
PWM3
DH2
DH1
PSI
CLKEN
t
BLANK
20
µs typ
t
BLANK
20
µs typ
BLANK HIGH-Z
PWM3 THREE-STATE
180
° OUT-OF-PHASE
BLANK LOW
BLANK HIGH-Z
BLANK LOW
Figure 7. PSI Transition