Rainbow Electronics MAX17036 - Manual (Page 36)

MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
36 ______________________________________________________________________________________
The optimum high-side MOSFET trades the switching
losses with the conduction (R
DS(ON) ) losses over the
input voltage range. Ideally, the losses at V IN(MIN)
should be roughly equal to losses at V IN(MAX) , with
lower losses in between. If V IN does not vary over a
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Low-Side MOSFET Power Dissipation
For the low-side MOSFET (N
L
), the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than I
LOAD(MAX)
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, the circuit can be overdesigned to tolerate:
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a low-side MOSFET that has the lowest possible
on-resistance (R
DS(ON)
), comes in a moderate-sized
package (i.e., one or two thermally enhanced 8-pin SOs),
and is reasonably priced. Make sure that the DL gate dri-
ver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-to-
drain capacitor caused by the high-side MOSFET turning
on; otherwise, cross-conduction problems might occur
(see the
MOSFET Gate Drivers section).
The optional Schottky diode (D L ) should have a low for-
ward voltage and be able to handle the load current
per phase during the dead times.
Boost Capacitors
The boost capacitors (C BST ) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Select the boost capacitors to
avoid discharging the capacitor more than 200mV while
charging the high-side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one regulator, and Q
GATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (1)
FDS6298 n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6298 has a maximum gate charge of 19nC
(V
GS = 5V). Using the above equation, the required
boost capacitance would be:
Selecting the closest standard value; this example
requires a 0.1µF ceramic capacitor.
Current Limit and Slew-Rate Control
(TIME and ILIM)
TIME and ILIM are used to control the slew rate and
current limit. TIME regulates to a fixed 2.0V. The
MAX17030/MAX17036 use the TIME source current to
set the slew rate (dV
TARGET
/dt). The higher the source
current, the faster the output-voltage slew rate:
where R
TIME
is the sum of resistance values between
TIME and ground.
The ILIM voltage determines the valley current-sense
threshold. When ILIM = V
CC
, the controller uses the
22.5mV preset current-limit threshold. In an adjustable
design, ILIM is connected to a resistive voltage-
divider connected between TIME and ground. The dif-
ferential voltage between TIME and ILIM sets the cur-
rent-limit threshold (V
LIMIT
), so the valley current-sense
threshold:
This allows design flexibility since the DCR sense circuit
or sense resistor does not have to be adjusted to meet
the current limit as long as the current-sense voltage
never exceeds 50mV. Keeping V
LIMIT
between 20mV to
40mV leaves room for future current-limit adjustment.
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
LOAD(MAX) minus
half the ripple current; therefore:
I I
LIR
VALLEY LOAD MAX
> −
⎛
⎝⎜
⎞
⎠⎟ ( )
1
2
V
V V
LIMIT
TIME ILIM =
−
10
dV dt mV µs
k
R
TARGET
TIME
= ×
⎛
⎝⎜ ⎞
⎠⎟
12 5
71 5
.
.
Ω
C
nC
mV
µF
BST
= × =
1 10
200
0 05 .
C
N Q
mV
BST
GATE =
×
200
I I
I
LOAD TOTAL VALLEY MAX
INDUCTOR = +
⎛
⎝⎜ ⎞
⎠⎟
η
( )
∆
2
( )
( ) = + η
TOTAL VALLEY MAX
LOAD MAX
I
I LIR
2 2
⎛
⎝⎜ ⎞
⎠⎟
PD (NL Resistive) = 1 −
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
V
V
OUT
IN MAX ( )
⎤⎤
⎦
⎥
⎥
⎛
⎝⎜ ⎞
⎠⎟
I
R
LOAD
TOTAL
DS ON η
2
( )