Rainbow Electronics MAX17036 User Manual
Page 27
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
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27
Suspend Mode
When the processor enters low-power deeper sleep
mode, the IMVP-6.5 CPU sets the VID DAC code to a
lower output voltage and drives DPRSLPVR high. The
MAX17030/MAX17036 respond by slewing the internal
target voltage to the new DAC code, switching to single-
phase operation, and letting the output voltage gradual-
ly drift down to the deeper sleep voltage. During the
transition, the MAX17030/MAX17036 blank both the
upper and lower PWRGD and CLKEN thresholds until
20µs after the internal target reaches the deeper sleep
voltage. Once the 20µs timer expires, the MAX17030/
MAX17036 reenable the lower PWRGD and CLKEN
threshold, but keep the upper threshold blanked.
Output-Voltage-Transition Timing
At the beginning of an output-voltage transition, the
MAX17030/MAX17036 blank both PWRGD thresholds,
preventing the PWRGD open-drain output from chang-
ing states during the transition. The controller enables
the lower PWRGD threshold approximately 20µs after
the slew-rate controller reaches the target output volt-
age, but the upper PWRGD threshold is enabled only if
the controller remains in forced-PWM operation. If the
controller enters pulse-skipping operation, the upper
PWRGD threshold remains blanked. The slew rate (set
by resistor R
TIME
) must be set fast enough to ensure
that the transition can be completed within the maxi-
mum allotted time.
The MAX17030/MAX17036 automatically control the cur-
rent to the minimum level required to complete the transi-
tion. The total transition time depends on R
TIME
, the
voltage difference, and the accuracy of the slew-rate
controller (C
SLEW
accuracy). The slew rate is not depen-
dent on the total output capacitance, as long as the
surge current is less than the current limit. For all dynam-
ic VID transitions, the transition time (t
TRAN
) is given by:
where dV
TARGET
/dt = 12.5mV/µs
× 71.5kΩ/R
TIME
is the
slew rate, V
OLD
is the original output voltage, and V
NEW
is the new target voltage. See TIME Slew-Rate
Accuracy in the
Electrical Characteristics
for slew-rate
limits. For soft-start and shutdown, the controller auto-
matically reduces the slew rate to 1/4.
The average inductor current per phase required to
make an output-voltage transition is:
where dV
TARGET
/dt is the required slew rate, C
OUT
is
the total output capacitance, and
η
TOTAL
is the number
of active phases.
Deeper Sleep Transitions
When DPRSLPVR goes high, the MAX17030/MAX17036
immediately disable phases 2 and 3 (DH2, DL2 forced
low, PWM3 three-state, DRSKP low), and enter pulse-
skipping operation (see Figures 5 and 6). If the VIDs are
set to a lower voltage setting, the output drops at a rate
determined by the load and the output capacitance. The
internal target still ramps as before, and PWRGD
remains blanked high impedance until 20µs after the
output voltage reaches the internal target. Once this
time expires, PWRGD monitors only the lower threshold:
•
Fast C4E Deeper Sleep Exit: When exiting deeper
sleep (DPRSLPVR pulled low) while the output volt-
age still exceeds the deeper sleep voltage, the
MAX17030/MAX17036 quickly slew (50mV/µs min
regardless of R
TIME
setting) the internal target volt-
age to the DAC code provided by the processor as
long as the output voltage is above the new target.
The controller remains in skip mode until the output
voltage equals the internal target. Once the internal
target reaches the output voltage, phase 2 is
enabled. The controller blanks PWRGD and CLKEN
(forced high impedance) until 20µs after the transi-
tion is completed. See Figure 5.
•
Standard C4 Deeper Sleep Exit: When exiting
deeper sleep (DPRSLPVR pulled low) while the out-
put voltage is regulating to the deeper sleep volt-
age, the MAX17030/MAX17036 immediately
activate all enabled phases and ramp the output
voltage to the LFM DAC code provided by the
processor at the slew rate set by R
TIME
. The con-
troller blanks PWRGD and CLKEN (forced high
impedance) until 20µs after the transition is com-
pleted. See Figure 6.
I
C
dV
dt
L
OUT
TOTAL
TARGET
≅
×
(
)
η
t
V
V
dV
dt
TRAN
NEW
OLD
TARGET
=
−
(
)