Rainbow Electronics MAX17036 User Manual
Page 34
MAX17030/MAX17036
1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
34
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Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. The core
must not to saturate at the peak inductor current (I
PEAK
):
Output Capacitor Selection
Output capacitor selection is determined by the con-
troller stability requirements, and the transient soar and
sag requirements of the application.
Output Capacitor ESR
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
In CPU V
CORE
converters and other applications where
the output is subject to large load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to finite capacitance:
The output ripple voltage of a step-down controller
equals the total inductor ripple current multiplied by the
output capacitor’s ESR. When operating multiphase
systems out-of-phase, the peak inductor currents of
each phase are staggered, resulting in lower output rip-
ple voltage by reducing the total inductor ripple current.
For multiphase operation, the maximum ESR to meet
ripple requirements is:
where η
TOTAL
is the total number of active phases and
f
SW
is the switching frequency per phase. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usu-
ally selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V
SAG
and V
SOAR
from causing prob-
lems during load transients. Generally, once enough
capacitance is added to meet the overshoot require-
ment, undershoot at the rising load edge is no longer a
problem (see the V
SAG
and V
SOAR
equations in the
Transient Response
section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
where:
and:
where C
OUT
is the total output capacitance, R
ESR
is the
total equivalent series resistance, R
DROOP
is the volt-
age-positioning gain, and R
PCB
is the parasitic board
resistance between the output capacitors and sense
resistors.
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard application circuit, the ESR needed to support
a 30mV
P-P
ripple is 30mV/(40A x 0.3) = 2.5m
Ω. Four
330µF/2.5V Panasonic SP (type SX) capacitors in paral-
lel provide 1.5m
Ω (max) ESR. With a 2mΩ droop and
0.5m
Ω PCB resistance, the typical combined ESR
results in a zero at 30kHz.
Ceramic capacitors have a high ESR zero frequency, but
applications with significant voltage positioning can take
advantage of their size and low ESR. When using only
ceramic output capacitors, output overshoot (V
SOAR
)
typically determines the minimum output capacitance
requirement. Their relatively low capacitance value
favors high switching-frequency operation with small
inductor values to minimize the energy transferred from
inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is not
enough voltage ramp in the output-voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
R
R
R
R
EFF
ESR
DROOP
PCB
=
+
+
f
R
C
ESR
EFF
OUT
=
1
2
π
f
f
ESR
SW
≤
π
R
V f
L
V
V
V
V
ESR
IN SW
IN
TOTAL OUT
OUT
RI
≤
−
(
)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
η
P
PPLE
R
R
V
I
ESR
PCB
STEP
LOAD MAX
+
(
)
≤
∆
(
)
I
I
LIR
PEAK
LOAD MAX
TOTAL
=
⎛
⎝⎜
⎞
⎠⎟
+
⎛
⎝⎜
⎞
⎠⎟
(
)
η
1
2