Rainbow Electronics DS2181A - Manual (Page 11)

DS2181A
041995 11/32
CCS SIGNALLING
CCS (selected when TCR.5 = 1 and/or when RCR.1 = 1)
utilizes all bit positions of timeslot 16 in every frame for
message-oriented signalling data transmission. In CCS
mode one can use either timeslot 16 or any one of the
other 30 data channels for message-oriented signalling.
The CCS mode has no multiframe structure and the in-
sertion of CAS multiframe alignment, distant multiframe
alarm and/or extra bits into timeslot 16 is disabled.
TSER is the source of timeslot 16 data.
CRC4 CODING
The need for enhanced error monitoring capability and
additional protection against emulators of the frame
alignment word has led to the development of a cyclic
redundancy check (CRC) procedure. When enabled via
CCR.2 and/or CCR.3, CRC4 coding replaces the inter-
national bit positions in frames 0 through 12 and 14 with
a CRC4 multiframe alignment pattern and associated
checksum words. The CRC4 multiframe must begin
with a frame containing the frame alignment signal
(CCR.6 = 0). A rising edge at TMSYNC establishes the
CRC4 multiframe alignment (TMSYNC will also estab-
lish outgoing CAS multiframe alignment if enabled via
TCR.5).
Incoming CRC4 multiframe alignment is indicated by
RCSYNC. Detected CRC4 checksum errors are re-
ported at output RFER and logged in the CECR.
RECEIVE SYNCHRONIZER
The fixed characteristics of the receive synchronizer
may be modified by use of programmable characteris-
tics resident in the RCR and CCR. Sync criteria must be
met before synchronization is declared. Resync criteria
establish error occurrences which will cause an auto-re-
sync event when enabled (RCR.1 = 0).
The receive synchronizer searches for the frame align-
ment pattern first. Once identified, the output timing set
associated with the framing pattern (all outputs except
RCSYNC and RMSYNC) is updated to that new align-
ment. If enabled, the synchronizer then begins CAS
and/or CRC4 multiframe search; outputs RMSYNC
and/or RCSYNC are then updated. Output RLOS is held
high during the entire resync process, then transitions
low after the last output timing update indicating resync
is complete. For more details about the receive syn-
chronizer, see the separate DS2181A CEPT Transceiv-
er Application Note.
FIXED FRAME SYNC CRITERIA
Valid frame sync is assumed when the correct frame
alignment signal is present in frame N and frame N + 2
and not present in frame N + 1 (bit 2 of timeslot 0 of
Frame N + 1 is also checked for 1). CAS and/or CRC4
multiframe alignment search is initiated when the frame
search is complete if enabled via RCR.5 and/or CCR.2.
FIXED CAS MULTIFRAME SYNC CRITERIA
CAS multiframe sync is declared when the multiframe
alignment pattern is properly detected and timeslot 16 of
the previous frame contains code other than zeros. If no
valid pattern can be found in 12 to 14 milliseconds (no
time out period exists if CCR.1=1 or TEST=1), frame
search is restarted .
FIXED CRC4 MULTIFRAME SYNC CRITERIA
CRC4 multiframe sync is declared if at least two valid
CRC4 multiframe alignment signals are found within 12
to 14 milliseconds (8 ms if CCR.1=1 or TEST=1) after
frame alignment is completed. If not found within 12 to
14 milliseconds (8 ms if CCR.1=1 or TEST=1), frame
search is restarted. The search for the multiframe align-
ment signal is performed in timeslot 0 of frames not con-
taining the frame alignment signal.
FIXED FRAME RESYNC CRITERIA
When enabled via RCR.1, the device will automatically
initiate frame search whenever the frame alignment
word is received in error three consecutive times.
FIXED CAS MULTIFRAME RESYNC CRITERIA
When enabled via RCR.1, the device will automatically
initiate frame search whenever two consecutive CAS
multiframe alignment words are received in error.
FIXED CRC4 RESYNC CRITERIA
If CCR.1=1 or if the TEST pin is tied high, then the
DS2181A will initiate the resync at the FAS level if 915 or
more CRC4 words out of 1000 are received in error.
CAS SIGNALLING SOURCE
CAS applications sample signalling data at TSER when
TCR.6 = 0; an on-chip data multiplexer accepts chan-
nel-associated data input at TSD when TCR.6 = 1. The
data multiplexer must be disabled (TCR.6 = 0) when the
CCS mode is enabled (TCR.5 = 1).