Rainbow Electronics DS2181A - Manual (Page 9)

DS2181A
041995 9/32
CCR: COMMON CONTROL REGISTER Figure 5
(MSB) (LSB)
– TAFP THDE RHDE TCE RCE SAS LLB
SYMBOL POSITION NAME AND DESCRIPTION
– CCR.7 Reserved; must be 0 for proper operation.
TAFP CCR.6 Transmit Align Frame Position 1
When clear, the CAS multiframe begins with a frame containing the frame
alignment signal. When set, the CAS multiframe begins with a frame not
containing the frame alignment signal.
THDE CCR.5 Transmit HDB3 Enable
0 = Outgoing data at TPOS and TNEG is AMI coded.
1 = Outgoing data at TPOS and TNEG is HDB3 coded.
RHDE CCR.4 Receive HDB3 Enable
0 = Incoming data at RPOS and RNEG is AMI coded.
1 = Incoming data is RPOS and RNEG is HDB3 coded.
TCE CCR.3 Transmit CRC4 Enable
When set, outgoing international bit positions in frames 0 through 12 and 14
are replaced by CRC4 multiframe alignment and checksum words.
RCE CCR.2 Receive CRC4 Enable
0 = Disable CRC4 multiframe synchronizer.
1 = Enable CRC4 synchronizer; search for CRC4 multiframe alignment
once frame alignment complete.
SAS CCR.1 Sync Algorithm Select
0 = Use old DS2181 sync algorithm
1 = Use new DS2181A sync algorithm
LLB CCR.0 Local Loopback
0 = Normal operation.
1 = Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG, and RCLK.
NOTES:
1. This bit must be cleared when CRC4 multiframe mode is enabled (CCR.3 = 1); its state does not affect CCS
framing (RCR.5 = 1).
2. CCR is considered a receive register and operates from RCLK and SCLK.