Rainbow Electronics DS2181A User Manual
Page 18
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DS2181A
041995 18/32
RECEIVE MULTIFRAME TIMING Figure 15
DATA VALID
FOR TIMESLOT 1
RCLK
RCHCLK
RSD
A
B
D
C
FRAME 2
TIMESLOT 1
TIMESLOT 18
DATA VALID
FOR TIMESLOT 18
NOT VALID
NOT VALID
A
B
C
D
RECEIVE TIMING
The receive side output timing set is identical to that
found on the transmit side. The user can tie receive out-
puts directly to the transmit inputs for drop and insert
applications. The received data of RPOS, RNEG ap-
pear at RSER after six RCLK delays, without any
change except for the HDB3-to-NRZ conversion when
HDB3 is enabled.
NOTE:
1. The CAS multiframe can start with an align or non-align frame. The CRC4 multiframe always starts with an
align frame.
RSD TIMING Figure 16
0
RFSYNC
FRAME #
RAF
RCSYNC
RMSYNC
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
15
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