Rainbow Electronics DS2181A - Manual (Page 2)

DS2181A
041995 2/32
The hardware mode is intended for preliminary system
prototyping and/or retrofitting into existing systems. This mode requires no host processor and disables
special features available in the processor mode.
DS2181A BLOCK DIAGRAM Figure 1
TCLK
TFSYNC
TMSYNC
TMO
TAF
TSTS
TCHCLK
TRANSMIT
TIMING
ALIGN WORD
GENERATOR
ALARM
GENERATOR
DATA
SELECTOR
HDB3
CODER
TSER
TSD
TIND
TXD
TPOS
TNEG
SERIAL PORT/
HARDWARE
MODE CONTROL
LOGIC
CONTROL, STATUS AND ALARM
REGISTERS
LOOPBACK
SPS
CS
SCLK
SDI
SDO
INT
RDMA
RBV
RRA
RCL
RFER
RLOS
RPOS
RNEG
RCLK
TEST
RST
VDD
VSS
HDB3
DECODER
RECEIVE
SYNCHRONIZER/
SYNC CONTROLLER
RECEIVE TIMING
ALARM DETECTION
DATA DEMUX
RSER
RSD
RFSYNC
RMSYNC
RCSYNC
RAF
RSTS
RCHCLK