Rainbow Electronics DS2181A - Manual (Page 6)

DS2181A
041995 6/32
SERIAL PORT INTERFACE
Pins 14 through 18 of the DS2181A serve as a micropro-
cessor/microcontroller-compatible serial port. Fourteen
on-chip registers allow the user to update operational
characteristics and monitor device status via a host con-
troller, minimizing hardware interfaces.
Port read/write timing is unrelated to the chip transmit
and receive timing, allowing asynchronous reads and/
or writes by the host. The timing set is identical to that of
8051-type microcontrollers operating in serial port
mode 0. For proper operation of the port and the trans-
mit and receive registers, the user should provide TCLK
and RCLK as well as SCLK.
ADDRESS/COMMAND
An address/command byte write must precede any
read or write of the port registers. The first bit written
(LSB) of the address/command byte specifies read or
write. The following nibble identifies register address.
The next two bits are reserved and must be set to zero
for proper operation. The last bit of the address/com-
mand word enables the burst mode when set; the burst
mode allows consecutive reading or writing of all regis-
ter data. Data is written to and read from the port LSB
first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the CS input
low. Data is sampled on the rising edge of SCLK. Data is
output on the falling edge of SCLK and held to the next
falling edge. All data transfers are terminated and SDO
tri-stated when CS returns to high.
CLOCKS
To access the serial port registers both TCLK and RCLK
are required along with the SCLK. The TCLK and RCLK
are used to internally access the transmit and receive
registers, respectively. The CCR is considered a re-
ceive register for this purpose.
DATA I/O
Following the eight SCLK cycles that input the address/
command byte, data at SDI is strobed into the ad-
dressed register on the next eight SCLK cycles (register
write) or data is presented at SDO on the next eight
SCLK cycles (register read). SDO is tri-stated during
writes and may be tied to SDI in applications where the
host processor has bidirectional I/O capability.
BURST MODE
The burst mode allows all on-chip registers to be con-
secutively read or written by the host processor. This
feature minimizes device initialization time on system
power-up or reset. Burst mode is initiated when ACB.7
is set and the address nibble is 0000.
All registers must
be read or written during the burst mode. If CS transi-
tions high before the burst is complete, data validity is
not guaranteed.