Rainbow Electronics DS2181A - Manual (Page 23)

RCLK
RCHCLK
RSTS
RFER 1
DS2181A
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RRA
The remote alarm output transitions high when a remote
alarm is detected. A high-low transition indicates the
alarm condition has been cleared. The alarm condition
is defined as bit 3 of time slot 0 set for three consecutive
non-align frames. The alarm state is cleared when bit 3
has been clear for three consecutive non-align frames.
The RRA bit (RSR.7) is a latched version of the RRA
output.
RBV
RBV pulses high when the accused bit emerges at
RSER. RBV will return low when RCLK goes low. Bipo-
lar violations are also logged in the BVCR. The RBV pin
provides a pulse for every violation which can be
counted externally.
RDMA
RDMA transitions high when bit 6 of timeslot 16 in frame
0 is set for three consecutive occasions and returns low
when the bit is clear for three consecutive occasions.
The RDMA bit (RSR.6) is a latched version of the RDMA
output.
RCL
RCL transitions high after 32 consecutive zeros appear
at RPOS and RNEG; it goes low at the next one occur-
rence.
RFER
The RFER output transitions high when received frame
alignment, CAS multiframe alignment and/or CRC4
code words are in error. The FECR and CECR log error
events reported at this output. FECR logs only the frame
alignment word errors. CECR logs CRC4 code word er-
rors.
To complement the on-chip error logging capabilities of
the DS2181A, the system designer can use off-chip log-
ic gated by receive side outputs RCHCLK, RAF, RSTS
and RCSYNC to demux error states present at RFER.
See the separate DS2181A CEPT Transceiver Application
Note for more details.
RFER OUTPUT TIMING FOR ALL ERROR CONDITIONS Figure 23
RFSYNC
RAF
RCSYNC
RMSYNC
1 2 3 4
RFER
CAS MULTIFRAME ALIGNMENT ERROR Figure 24